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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-12 13:43:26 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | a427c83633924d2bc9485d30c2658dd9fc44b9f1 (patch) | |
| tree | 62195579c7977f4e32db4234fce39b8d221e82a7 /target | |
| parent | eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf (diff) | |
| download | qemu-a427c83633924d2bc9485d30c2658dd9fc44b9f1.zip qemu-a427c83633924d2bc9485d30c2658dd9fc44b9f1.tar.gz qemu-a427c83633924d2bc9485d30c2658dd9fc44b9f1.tar.bz2 | |
target/riscv: Hoist second stage mode change to callers
Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_helper.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 38bd83f..5753e4e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - if (first_stage == false) { - /* - * We are in stage 2 translation, this is similar to stage 1. - * Stage 2 is always taken as U-mode - */ - mode = PRV_U; - } - if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -890,7 +882,7 @@ restart: /* Do the second stage translation on the base PTE address. */ int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, base, NULL, MMU_DATA_LOAD, - mmu_idx, false, true, + MMUIdx_U, false, true, is_debug); if (vbase_ret != TRANSLATE_SUCCESS) { @@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, im_address = pa; ret = get_physical_address(env, &pa, &prot2, im_address, NULL, - access_type, mmu_idx, false, true, + access_type, MMUIdx_U, false, true, false); qemu_log_mask(CPU_LOG_MMU, |