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| author | Jiaxi Chen <jiaxi.chen@linux.intel.com> | 2023-03-03 14:59:09 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-04-28 12:50:34 +0200 |
| commit | 99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5 (patch) | |
| tree | 867e9860d0c607646a3b5bf602cb22cd43b6bffa /target | |
| parent | a9ce107fd0f2017af84255a9cf6542fa3eb3e214 (diff) | |
| download | qemu-99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5.zip qemu-99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5.tar.gz qemu-99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5.tar.bz2 | |
target/i386: Add support for AMX-FP16 in CPUID enumeration
Latest Intel platform Granite Rapids has introduced a new instruction -
AMX-FP16, which performs dot-products of two FP16 tiles and accumulates
the results into a packed single precision tile. AMX-FP16 adds FP16
capability and allows a FP16 GPU trained model to run faster without
loss of accuracy or added SW overhead.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 21]
Add CPUID definition for AMX-FP16.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-3-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 67210ff..841c407 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -879,7 +879,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "amx-fp16", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d5843c1..7deb37e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -915,6 +915,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EAX_FSRS (1U << 11) /* Fast Short REP CMPS/SCAS */ #define CPUID_7_1_EAX_FSRC (1U << 12) +/* Support Tile Computational Operations on FP16 Numbers */ +#define CPUID_7_1_EAX_AMX_FP16 (1U << 21) /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) |