diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:44:56 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:19:35 +0100 |
| commit | 7a867dd57a480998361f5cc61ce83f342a020b0e (patch) | |
| tree | fdd6199b7635562db63867acb3d7c68ea8b11bd1 /target | |
| parent | 63b38f6c85acd312c2cab68554abf33adf4ee2b3 (diff) | |
| download | qemu-7a867dd57a480998361f5cc61ce83f342a020b0e.zip qemu-7a867dd57a480998361f5cc61ce83f342a020b0e.tar.gz qemu-7a867dd57a480998361f5cc61ce83f342a020b0e.tar.bz2 | |
target/arm: Handle SME in aarch64_cpu_dump_state
Dump SVCR, plus use the correct access check for Streaming Mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae6dca2..9c58be8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -878,6 +878,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) int i; int el = arm_current_el(env); const char *ns_status; + bool sve; qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); for (i = 0; i < 32; i++) { @@ -904,6 +905,12 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) el, psr & PSTATE_SP ? 'h' : 't'); + if (cpu_isar_feature(aa64_sme, cpu)) { + qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", + env->svcr, + (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), + (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); + } if (cpu_isar_feature(aa64_bti, cpu)) { qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); } @@ -918,7 +925,15 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { + if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { + sve = sme_exception_el(env, el) == 0; + } else if (cpu_isar_feature(aa64_sve, cpu)) { + sve = sve_exception_el(env, el) == 0; + } else { + sve = false; + } + + if (sve) { int j, zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { |