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authorFrank Chang <frank.chang@sifive.com>2022-01-18 09:45:06 +0800
committerAlistair Francis <alistair.francis@wdc.com>2022-01-21 15:52:56 +1000
commit494104093fafab12208a8f1f0cb2ab5f5c8c7035 (patch)
tree8aa14fe1e5071ea624b4d545a242fad9fed57f4d /target
parentc7a26fb2f6bafd45b983d81d180f624c0e8c4d2b (diff)
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target/riscv: rvv-1.0: Add Zve64f support for load and store insns
All Zve* extensions support all vector load and store instructions, except Zve64* extensions do not support EEW=64 for index values when XLEN=32. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/insn_trans/trans_rvv.c.inc19
1 files changed, 15 insertions, 4 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b47729..0bf41aa 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
uint8_t eew)
{
int8_t emul = eew - s->sew + s->lmul;
- return (emul >= -3 && emul <= 3) &&
- require_align(vs2, emul) &&
- require_align(vd, s->lmul) &&
- require_nf(vd, nf, s->lmul);
+ bool ret = (emul >= -3 && emul <= 3) &&
+ require_align(vs2, emul) &&
+ require_align(vd, s->lmul) &&
+ require_nf(vd, nf, s->lmul);
+
+ /*
+ * All Zve* extensions support all vector load and store instructions,
+ * except Zve64* extensions do not support EEW=64 for index values
+ * when XLEN=32. (Section 18.2)
+ */
+ if (get_xl(s) == MXL_RV32) {
+ ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+ }
+
+ return ret;
}
/*