diff options
author | Anup Patel <apatel@ventanamicro.com> | 2023-01-20 18:29:47 +0530 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:22 +1000 |
commit | 2cfb3b6c9b78fd9d47a2934ba53293c73c680406 (patch) | |
tree | 417dfe4a435f6c9c63897d715db1e8472fe6ee83 /target | |
parent | 32c435a1ae9be183a309fb102d0fc38a4d2cd669 (diff) | |
download | qemu-2cfb3b6c9b78fd9d47a2934ba53293c73c680406.zip qemu-2cfb3b6c9b78fd9d47a2934ba53293c73c680406.tar.gz qemu-2cfb3b6c9b78fd9d47a2934ba53293c73c680406.tar.bz2 |
target/riscv: Update VS timer whenever htimedelta changes
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/csr.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 62e6c4a..fa17d77 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3045,6 +3045,8 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno, static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -3054,6 +3056,12 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, } else { env->htimedelta = val; } + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } @@ -3071,11 +3079,19 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } |