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| author | Yifei Jiang <jiangyifei@huawei.com> | 2022-01-12 16:13:25 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 10f1ca27e0fe9930d372591cd5f302e7249aa705 (patch) | |
| tree | 9cce9588d0bd3ff352633df705cbc41a63a33b86 /target | |
| parent | 4eb471258bd0e331678bece4c894c477928b3b0b (diff) | |
| download | qemu-10f1ca27e0fe9930d372591cd5f302e7249aa705.zip qemu-10f1ca27e0fe9930d372591cd5f302e7249aa705.tar.gz qemu-10f1ca27e0fe9930d372591cd5f302e7249aa705.tar.bz2 | |
target/riscv: Add host cpu type
'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-10-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 15 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 53b0524..32879f1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -235,6 +235,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) } #endif +#if defined(CONFIG_KVM) +static void riscv_host_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; +#if defined(TARGET_RISCV32) + set_misa(env, MXL_RV32, 0); +#elif defined(TARGET_RISCV64) + set_misa(env, MXL_RV64, 0); +#endif +} +#endif + static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -847,6 +859,9 @@ static const TypeInfo riscv_cpu_type_infos[] = { .class_init = riscv_cpu_class_init, }, DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(CONFIG_KVM) + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), +#endif #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8fa6fdc..73ced21 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -47,6 +47,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 |