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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2018-05-16 00:04:54 +0200
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2018-05-29 09:35:14 +0200
commit05a9a6519c9127b5fb0b13481ecc0e72331c8a38 (patch)
treee821c82a5d86d5c42cf9b98a765350399c258142 /target
parent3924a9aa02fa00a256ddcfe2d6a08bc410ddcaaf (diff)
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target-microblaze: dec_msr: Plug a temp leak
Plug a temp leak. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
-rw-r--r--target/microblaze/translate.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 7475003..756d901 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -516,12 +516,17 @@ static void dec_msr(DisasContext *dc)
#if !defined(CONFIG_USER_ONLY)
/* Catch read/writes to the mmu block. */
if ((sr & ~0xff) == 0x1000) {
+ TCGv_i32 tmp_sr;
+
sr &= 7;
+ tmp_sr = tcg_const_i32(sr);
LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
- if (to)
- gen_helper_mmu_write(cpu_env, tcg_const_i32(sr), cpu_R[dc->ra]);
- else
- gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_i32(sr));
+ if (to) {
+ gen_helper_mmu_write(cpu_env, tmp_sr, cpu_R[dc->ra]);
+ } else {
+ gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_sr);
+ }
+ tcg_temp_free_i32(tmp_sr);
return;
}
#endif