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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-21 23:26:16 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-05 15:17:35 +0000 |
| commit | dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6 (patch) | |
| tree | a974c9f3f25a9228af58d7576a6a9f55d44a60a5 /target | |
| parent | 6e937ba7f8fb90d66cb3781f7fed32fb4239556a (diff) | |
| download | qemu-dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6.zip qemu-dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6.tar.gz qemu-dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6.tar.bz2 | |
target/arm/cpu: Update coding style to make checkpatch.pl happy
We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210221222617.2579610-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2666d43..6facb66 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1972,7 +1972,8 @@ static void cortex_a8_initfn(Object *obj) } static const ARMCPRegInfo cortexa9_cp_reginfo[] = { - /* power_control should be set to maximum latency. Again, + /* + * power_control should be set to maximum latency. Again, * default to 0 and set by private hook */ { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, @@ -2009,7 +2010,8 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); - /* Note that A9 supports the MP extensions even for + /* + * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). */ @@ -2046,7 +2048,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { MachineState *ms = MACHINE(qdev_get_machine()); - /* Linux wants the number of processors from here. + /* + * Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ return ((ms->smp.cpus - 1) << 24) | (1 << 23); @@ -2093,7 +2096,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_mmfr1 = 0x40000000; cpu->isar.id_mmfr2 = 0x01240000; cpu->isar.id_mmfr3 = 0x02102211; - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ cpu->isar.id_isar0 = 0x02101110; |