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author | Taylor Simpson <tsimpson@quicinc.com> | 2021-04-08 20:07:29 -0500 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-05-01 08:31:43 -0700 |
commit | d799f8ad08742e9c042e208d970febf87a2c4901 (patch) | |
tree | a889433951a3bb58e79869b9ebfa113dd3378b60 /target | |
parent | 5f261764cec291bb159ffecd291a1bfd6800215b (diff) | |
download | qemu-d799f8ad08742e9c042e208d970febf87a2c4901.zip qemu-d799f8ad08742e9c042e208d970febf87a2c4901.tar.gz qemu-d799f8ad08742e9c042e208d970febf87a2c4901.tar.bz2 |
Hexagon (target/hexagon) TCG generation cleanup
Simplify TCG generation of hex_reg_written
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-2-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/hexagon/genptr.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 7481f4c..87f5d92 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -35,7 +35,6 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t num) static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) { - TCGv one = tcg_const_tl(1); TCGv zero = tcg_const_tl(0); TCGv slot_mask = tcg_temp_new(); @@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, val, hex_new_value[rnum]); #if HEX_DEBUG - /* Do this so HELPER(debug_commit_end) will know */ - tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero, - one, hex_reg_written[rnum]); + /* + * Do this so HELPER(debug_commit_end) will know + * + * Note that slot_mask indicates the value is not written + * (i.e., slot was cancelled), so we create a true/false value before + * or'ing with hex_reg_written[rnum]. + */ + tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); + tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); #endif - tcg_temp_free(one); tcg_temp_free(zero); tcg_temp_free(slot_mask); } |