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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-02-22 15:51:56 -0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 13:47:08 -0800 |
| commit | d4ea71170432fef9e8394ab33eac3cdc3a9540d3 (patch) | |
| tree | 31f734dd321fb9b3fe4b48fcfa881387e4f88854 /target | |
| parent | 627634031092e1514f363fd8659a579398de0f0e (diff) | |
| download | qemu-d4ea71170432fef9e8394ab33eac3cdc3a9540d3.zip qemu-d4ea71170432fef9e8394ab33eac3cdc3a9540d3.tar.gz qemu-d4ea71170432fef9e8394ab33eac3cdc3a9540d3.tar.bz2 | |
target/riscv: introduce riscv_cpu_cfg()
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230222185205.355361-2-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 31537fc..7ee22cb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) +static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +{ + return &env_archcpu(env)->cfg; +} + #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else |