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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2021-06-01 18:46:45 -0300 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-06-03 18:10:31 +1000 |
| commit | bbc443cf65e3bf580df9dd8d2cd3f27154309add (patch) | |
| tree | 0d8e87d4fe3938ed325e81a7b17e9a0311195bb1 /target | |
| parent | fe43ba9721f36e47e09779682c3525659c6818f0 (diff) | |
| download | qemu-bbc443cf65e3bf580df9dd8d2cd3f27154309add.zip qemu-bbc443cf65e3bf580df9dd8d2cd3f27154309add.tar.gz qemu-bbc443cf65e3bf580df9dd8d2cd3f27154309add.tar.bz2 | |
target/ppc: powerpc_excp: Move lpes code to where it is used
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210601214649.785647-2-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/excp_helper.c | 47 |
1 files changed, 25 insertions, 22 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0441805..5ea8503 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -333,7 +333,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) CPUPPCState *env = &cpu->env; target_ulong msr, new_msr, vector; int srr0, srr1, asrr0, asrr1, lev = -1; - bool lpes0; qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx " => %08x (%02x)\n", env->nip, excp, env->error_code); @@ -366,27 +365,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } /* - * Exception targeting modifiers - * - * LPES0 is supported on POWER7/8/9 - * LPES1 is not supported (old iSeries mode) - * - * On anything else, we behave as if LPES0 is 1 - * (externals don't alter MSR:HV) - */ -#if defined(TARGET_PPC64) - if (excp_model == POWERPC_EXCP_POWER7 || - excp_model == POWERPC_EXCP_POWER8 || - excp_model == POWERPC_EXCP_POWER9 || - excp_model == POWERPC_EXCP_POWER10) { - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - } else -#endif /* defined(TARGET_PPC64) */ - { - lpes0 = true; - } - - /* * Hypervisor emulation assistance interrupt only exists on server * arch 2.05 server or later. We also don't want to generate it if * we don't have HVB in msr_mask (PAPR mode). @@ -473,8 +451,32 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) msr |= env->error_code; break; case POWERPC_EXCP_EXTERNAL: /* External input */ + { + bool lpes0; + cs = CPU(cpu); + /* + * Exception targeting modifiers + * + * LPES0 is supported on POWER7/8/9 + * LPES1 is not supported (old iSeries mode) + * + * On anything else, we behave as if LPES0 is 1 + * (externals don't alter MSR:HV) + */ +#if defined(TARGET_PPC64) + if (excp_model == POWERPC_EXCP_POWER7 || + excp_model == POWERPC_EXCP_POWER8 || + excp_model == POWERPC_EXCP_POWER9 || + excp_model == POWERPC_EXCP_POWER10) { + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); + } else +#endif /* defined(TARGET_PPC64) */ + { + lpes0 = true; + } + if (!lpes0) { new_msr |= (target_ulong)MSR_HVB; new_msr |= env->msr & ((target_ulong)1 << MSR_RI); @@ -486,6 +488,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); } break; + } case POWERPC_EXCP_ALIGN: /* Alignment exception */ /* Get rS/rD and rA from faulting opcode */ /* |