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authorPeter Maydell <peter.maydell@linaro.org>2020-10-19 16:12:56 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-10-20 16:12:01 +0100
commit920f04fa3ea789f8f85a52cee5395b8887b56cf7 (patch)
tree635050ab3df6abb871fc452184d04c3a2ae7a813 /target
parent45f11876ae86128bdee27e0b089045de43cc88e4 (diff)
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target/arm: Don't allow BLX imm for M-profile
The BLX immediate insn in the Thumb encoding always performs a switch from Thumb to Arm state. This would be totally useless in M-profile which has no Arm decoder, and so the instruction does not exist at all there. Make the encoding UNDEF for M-profile. (This part of the encoding space is used for the branch-future and low-overhead-loop insns in v8.1M.) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-6-peter.maydell@linaro.org
Diffstat (limited to 'target')
-rw-r--r--target/arm/translate.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9f2201c..dc3a403 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7918,6 +7918,14 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{
TCGv_i32 tmp;
+ /*
+ * BLX <imm> would be useless on M-profile; the encoding space
+ * is used for other insns from v8.1M onward, and UNDEFs before that.
+ */
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+
/* For A32, ARM_FEATURE_V5 is checked near the start of the uncond block. */
if (s->thumb && (a->imm & 2)) {
return false;