diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-01 18:33:45 -0700 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2022-06-02 09:35:02 +0200 |
| commit | 79e1d527e13d35b976c947c48a70c23ef3586e76 (patch) | |
| tree | a7235442360471806fcce2f4fde86c3bfcd0a5d9 /target | |
| parent | abc098351e533de5ca0ed9c90901f9f4dac348fc (diff) | |
| download | qemu-79e1d527e13d35b976c947c48a70c23ef3586e76.zip qemu-79e1d527e13d35b976c947c48a70c23ef3586e76.tar.gz qemu-79e1d527e13d35b976c947c48a70c23ef3586e76.tar.bz2 | |
target/m68k: Raise the TRAPn exception with the correct pc
Rather than adjust the PC in all of the consumers, raise
the exception with the correct PC in the first place.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220602013401.303699-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target')
| -rw-r--r-- | target/m68k/op_helper.c | 9 | ||||
| -rw-r--r-- | target/m68k/translate.c | 2 |
2 files changed, 1 insertions, 10 deletions
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8decc61..d30f988 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -217,11 +217,6 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw) cpu_loop_exit(cs); return; } - if (cs->exception_index >= EXCP_TRAP0 - && cs->exception_index <= EXCP_TRAP15) { - /* Move the PC after the trap instruction. */ - retaddr += 2; - } } vector = cs->exception_index << 2; @@ -304,10 +299,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) /* Return from an exception. */ m68k_rte(env); return; - case EXCP_TRAP0 ... EXCP_TRAP15: - /* Move the PC after the trap instruction. */ - retaddr += 2; - break; } } diff --git a/target/m68k/translate.c b/target/m68k/translate.c index e4efd98..22e5379 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4860,7 +4860,7 @@ DISAS_INSN(wdebug) DISAS_INSN(trap) { - gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf)); + gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } static void gen_load_fcr(DisasContext *s, TCGv res, int reg) |