Merge tag 'pull-hex-20230421' of https://github.com/quic/qemu into staging

Hexagon update

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# gpg:                using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5  9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20230421' of https://github.com/quic/qemu:
  Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
  Hexagon (target/hexagon) Remove unused slot variable in helpers
  Hexagon (tests/tcg/hexagon) Move HVX test infra to header file
  Hexagon (target/hexagon) Updates to USR should use get_result_gpr
  Hexagon (target/hexagon) Add overrides for count trailing zeros/ones
  Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores
  Hexagon (target/hexagon) Remove redundant/unused macros
  Use black code style for python scripts
  Use f-strings in python scripts
  Hexagon (translate.c): avoid redundant PC updates on COF

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

24 files changed, 1428 insertions, 1193 deletions

diff --git a/target/hexagon/dectree.py b/target/hexagon/dectree.py
index 29467ec..3b32948 100755
--- a/target/hexagon/dectree.py
+++ b/target/hexagon/dectree.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -23,94 +23,109 @@ import re
 import sys
 import iset
 
-encs = {tag : ''.join(reversed(iset.iset[tag]['enc'].replace(' ', '')))
-    for tag in iset.tags if iset.iset[tag]['enc'] != 'MISSING ENCODING'}
+encs = {
+    tag: "".join(reversed(iset.iset[tag]["enc"].replace(" ", "")))
+    for tag in iset.tags
+    if iset.iset[tag]["enc"] != "MISSING ENCODING"
+}
 
-enc_classes = set([iset.iset[tag]['enc_class'] for tag in encs.keys()])
-subinsn_enc_classes = \
-    set([enc_class for enc_class in enc_classes \
-        if enc_class.startswith('SUBINSN_')])
-ext_enc_classes = \
-    set([enc_class for enc_class in enc_classes \
-        if enc_class not in ('NORMAL', '16BIT') and \
-           not enc_class.startswith('SUBINSN_')])
+enc_classes = set([iset.iset[tag]["enc_class"] for tag in encs.keys()])
+subinsn_enc_classes = set(
+    [enc_class for enc_class in enc_classes if enc_class.startswith("SUBINSN_")]
+)
+ext_enc_classes = set(
+    [
+        enc_class
+        for enc_class in enc_classes
+        if enc_class not in ("NORMAL", "16BIT") and not enc_class.startswith("SUBINSN_")
+    ]
+)
 
 try:
     subinsn_groupings = iset.subinsn_groupings
 except AttributeError:
     subinsn_groupings = {}
 
-for (tag, subinsn_grouping) in subinsn_groupings.items():
-    encs[tag] = ''.join(reversed(subinsn_grouping['enc'].replace(' ', '')))
+for tag, subinsn_grouping in subinsn_groupings.items():
+    encs[tag] = "".join(reversed(subinsn_grouping["enc"].replace(" ", "")))
 
-dectree_normal = {'leaves' : set()}
-dectree_16bit = {'leaves' : set()}
-dectree_subinsn_groupings = {'leaves' : set()}
-dectree_subinsns = {name : {'leaves' : set()} for name in subinsn_enc_classes}
-dectree_extensions = {name : {'leaves' : set()} for name in ext_enc_classes}
+dectree_normal = {"leaves": set()}
+dectree_16bit = {"leaves": set()}
+dectree_subinsn_groupings = {"leaves": set()}
+dectree_subinsns = {name: {"leaves": set()} for name in subinsn_enc_classes}
+dectree_extensions = {name: {"leaves": set()} for name in ext_enc_classes}
 
 for tag in encs.keys():
     if tag in subinsn_groupings:
-        dectree_subinsn_groupings['leaves'].add(tag)
+        dectree_subinsn_groupings["leaves"].add(tag)
         continue
-    enc_class = iset.iset[tag]['enc_class']
-    if enc_class.startswith('SUBINSN_'):
+    enc_class = iset.iset[tag]["enc_class"]
+    if enc_class.startswith("SUBINSN_"):
         if len(encs[tag]) != 32:
-            encs[tag] = encs[tag] + '0' * (32 - len(encs[tag]))
-        dectree_subinsns[enc_class]['leaves'].add(tag)
-    elif  enc_class == '16BIT':
+            encs[tag] = encs[tag] + "0" * (32 - len(encs[tag]))
+        dectree_subinsns[enc_class]["leaves"].add(tag)
+    elif enc_class == "16BIT":
         if len(encs[tag]) != 16:
-            raise Exception('Tag "{}" has enc_class "{}" and not an encoding ' +
-                            'width of 16 bits!'.format(tag, enc_class))
-        dectree_16bit['leaves'].add(tag)
+            raise Exception(
+                'Tag "{}" has enc_class "{}" and not an encoding '
+                + "width of 16 bits!".format(tag, enc_class)
+            )
+        dectree_16bit["leaves"].add(tag)
     else:
         if len(encs[tag]) != 32:
-            raise Exception('Tag "{}" has enc_class "{}" and not an encoding ' +
-                            'width of 32 bits!'.format(tag, enc_class))
-        if enc_class == 'NORMAL':
-            dectree_normal['leaves'].add(tag)
+            raise Exception(
+                'Tag "{}" has enc_class "{}" and not an encoding '
+                + "width of 32 bits!".format(tag, enc_class)
+            )
+        if enc_class == "NORMAL":
+            dectree_normal["leaves"].add(tag)
         else:
-            dectree_extensions[enc_class]['leaves'].add(tag)
+            dectree_extensions[enc_class]["leaves"].add(tag)
 
 faketags = set()
-for (tag, enc) in iset.enc_ext_spaces.items():
+for tag, enc in iset.enc_ext_spaces.items():
     faketags.add(tag)
-    encs[tag] = ''.join(reversed(enc.replace(' ', '')))
-    dectree_normal['leaves'].add(tag)
+    encs[tag] = "".join(reversed(enc.replace(" ", "")))
+    dectree_normal["leaves"].add(tag)
 
 faketags |= set(subinsn_groupings.keys())
 
+
 def every_bit_counts(bitset):
     for i in range(1, len(next(iter(bitset)))):
-        if len(set([bits[:i] + bits[i+1:] for bits in bitset])) == len(bitset):
+        if len(set([bits[:i] + bits[i + 1 :] for bits in bitset])) == len(bitset):
             return False
     return True
 
+
 def auto_separate(node):
-    tags = node['leaves']
+    tags = node["leaves"]
     if len(tags) <= 1:
         return
     enc_width = len(encs[next(iter(tags))])
-    opcode_bit_for_all = \
-        [all([encs[tag][i] in '01' \
-            for tag in tags]) for i in range(enc_width)]
-    opcode_bit_is_0_for_all = \
-        [opcode_bit_for_all[i] and all([encs[tag][i] == '0' \
-            for tag in tags]) for i in range(enc_width)]
-    opcode_bit_is_1_for_all = \
-        [opcode_bit_for_all[i] and all([encs[tag][i] == '1' \
-            for tag in tags]) for i in range(enc_width)]
-    differentiator_opcode_bit = \
-        [opcode_bit_for_all[i] and \
-         not (opcode_bit_is_0_for_all[i] or \
-         opcode_bit_is_1_for_all[i]) \
-            for i in range(enc_width)]
+    opcode_bit_for_all = [
+        all([encs[tag][i] in "01" for tag in tags]) for i in range(enc_width)
+    ]
+    opcode_bit_is_0_for_all = [
+        opcode_bit_for_all[i] and all([encs[tag][i] == "0" for tag in tags])
+        for i in range(enc_width)
+    ]
+    opcode_bit_is_1_for_all = [
+        opcode_bit_for_all[i] and all([encs[tag][i] == "1" for tag in tags])
+        for i in range(enc_width)
+    ]
+    differentiator_opcode_bit = [
+        opcode_bit_for_all[i]
+        and not (opcode_bit_is_0_for_all[i] or opcode_bit_is_1_for_all[i])
+        for i in range(enc_width)
+    ]
     best_width = 0
     for width in range(4, 0, -1):
         for lsb in range(enc_width - width, -1, -1):
-            bitset = set([encs[tag][lsb:lsb+width] for tag in tags])
-            if all(differentiator_opcode_bit[lsb:lsb+width]) and \
-                (len(bitset) == len(tags) or every_bit_counts(bitset)):
+            bitset = set([encs[tag][lsb : lsb + width] for tag in tags])
+            if all(differentiator_opcode_bit[lsb : lsb + width]) and (
+                len(bitset) == len(tags) or every_bit_counts(bitset)
+            ):
                 best_width = width
                 best_lsb = lsb
                 caught_all_tags = len(bitset) == len(tags)
@@ -118,33 +133,37 @@ def auto_separate(node):
         if best_width != 0:
             break
     if best_width == 0:
-        raise Exception('Could not find a way to differentiate the encodings ' +
-                         'of the following tags:\n{}'.format('\n'.join(tags)))
+        raise Exception(
+            "Could not find a way to differentiate the encodings "
+            + "of the following tags:\n{}".format("\n".join(tags))
+        )
     if caught_all_tags:
         for width in range(1, best_width):
             for lsb in range(enc_width - width, -1, -1):
-                bitset = set([encs[tag][lsb:lsb+width] for tag in tags])
-                if all(differentiator_opcode_bit[lsb:lsb+width]) and \
-                    len(bitset) == len(tags):
+                bitset = set([encs[tag][lsb : lsb + width] for tag in tags])
+                if all(differentiator_opcode_bit[lsb : lsb + width]) and len(
+                    bitset
+                ) == len(tags):
                     best_width = width
                     best_lsb = lsb
                     break
             else:
                 continue
             break
-    node['separator_lsb'] = best_lsb
-    node['separator_width'] = best_width
-    node['children'] = []
-    for value in range(2 ** best_width):
+    node["separator_lsb"] = best_lsb
+    node["separator_width"] = best_width
+    node["children"] = []
+    for value in range(2**best_width):
         child = {}
-        bits = ''.join(reversed('{:0{}b}'.format(value, best_width)))
-        child['leaves'] = \
-            set([tag for tag in tags \
-                if encs[tag][best_lsb:best_lsb+best_width] == bits])
-        node['children'].append(child)
-    for child in node['children']:
+        bits = "".join(reversed("{:0{}b}".format(value, best_width)))
+        child["leaves"] = set(
+            [tag for tag in tags if encs[tag][best_lsb : best_lsb + best_width] == bits]
+        )
+        node["children"].append(child)
+    for child in node["children"]:
         auto_separate(child)
 
+
 auto_separate(dectree_normal)
 auto_separate(dectree_16bit)
 if subinsn_groupings:
@@ -157,144 +176,173 @@ for dectree_ext in dectree_extensions.values():
 for tag in faketags:
     del encs[tag]
 
+
 def table_name(parents, node):
     path = parents + [node]
     root = path[0]
-    tag = next(iter(node['leaves']))
+    tag = next(iter(node["leaves"]))
     if tag in subinsn_groupings:
-        enc_width = len(subinsn_groupings[tag]['enc'].replace(' ', ''))
+        enc_width = len(subinsn_groupings[tag]["enc"].replace(" ", ""))
     else:
-        tag = next(iter(node['leaves'] - faketags))
+        tag = next(iter(node["leaves"] - faketags))
         enc_width = len(encs[tag])
-    determining_bits = ['_'] * enc_width
-    for (parent, child) in zip(path[:-1], path[1:]):
-        lsb = parent['separator_lsb']
-        width = parent['separator_width']
-        value = parent['children'].index(child)
-        determining_bits[lsb:lsb+width] = \
-            list(reversed('{:0{}b}'.format(value, width)))
+    determining_bits = ["_"] * enc_width
+    for parent, child in zip(path[:-1], path[1:]):
+        lsb = parent["separator_lsb"]
+        width = parent["separator_width"]
+        value = parent["children"].index(child)
+        determining_bits[lsb : lsb + width] = list(
+            reversed("{:0{}b}".format(value, width))
+        )
     if tag in subinsn_groupings:
-        name = 'DECODE_ROOT_EE'
+        name = "DECODE_ROOT_EE"
     else:
-        enc_class = iset.iset[tag]['enc_class']
+        enc_class = iset.iset[tag]["enc_class"]
         if enc_class in ext_enc_classes:
-            name = 'DECODE_EXT_{}'.format(enc_class)
+            name = "DECODE_EXT_{}".format(enc_class)
         elif enc_class in subinsn_enc_classes:
-            name = 'DECODE_SUBINSN_{}'.format(enc_class)
+            name = "DECODE_SUBINSN_{}".format(enc_class)
         else:
-            name = 'DECODE_ROOT_{}'.format(enc_width)
+            name = "DECODE_ROOT_{}".format(enc_width)
     if node != root:
-        name += '_' + ''.join(reversed(determining_bits))
+        name += "_" + "".join(reversed(determining_bits))
     return name
 
+
 def print_node(f, node, parents):
-    if len(node['leaves']) <= 1:
+    if len(node["leaves"]) <= 1:
         return
     name = table_name(parents, node)
-    lsb = node['separator_lsb']
-    width = node['separator_width']
-    print('DECODE_NEW_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))'.\
-        format(name, 2 ** width, lsb, width), file=f)
-    for child in node['children']:
-        if len(child['leaves']) == 0:
-            print('INVALID()', file=f)
-        elif len(child['leaves']) == 1:
-            (tag,) = child['leaves']
+    lsb = node["separator_lsb"]
+    width = node["separator_width"]
+    print(
+        "DECODE_NEW_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))".format(
+            name, 2**width, lsb, width
+        ),
+        file=f,
+    )
+    for child in node["children"]:
+        if len(child["leaves"]) == 0:
+            print("INVALID()", file=f)
+        elif len(child["leaves"]) == 1:
+            (tag,) = child["leaves"]
             if tag in subinsn_groupings:
-                class_a = subinsn_groupings[tag]['class_a']
-                class_b = subinsn_groupings[tag]['class_b']
-                enc = subinsn_groupings[tag]['enc'].replace(' ', '')
-                if 'RESERVED' in tag:
-                    print('INVALID()', file=f)
+                class_a = subinsn_groupings[tag]["class_a"]
+                class_b = subinsn_groupings[tag]["class_b"]
+                enc = subinsn_groupings[tag]["enc"].replace(" ", "")
+                if "RESERVED" in tag:
+                    print("INVALID()", file=f)
                 else:
-                    print('SUBINSNS({},{},{},"{}")'.\
-                        format(tag, class_a, class_b, enc), file=f)
+                    print(
+                        'SUBINSNS({},{},{},"{}")'.format(tag, class_a, class_b, enc),
+                        file=f,
+                    )
             elif tag in iset.enc_ext_spaces:
-                enc = iset.enc_ext_spaces[tag].replace(' ', '')
+                enc = iset.enc_ext_spaces[tag].replace(" ", "")
                 print('EXTSPACE({},"{}")'.format(tag, enc), file=f)
             else:
-                enc = ''.join(reversed(encs[tag]))
+                enc = "".join(reversed(encs[tag]))
                 print('TERMINAL({},"{}")'.format(tag, enc), file=f)
         else:
-            print('TABLE_LINK({})'.format(table_name(parents + [node], child)),
-                  file=f)
-    print('DECODE_END_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))'.\
-        format(name, 2 ** width, lsb, width), file=f)
+            print("TABLE_LINK({})".format(table_name(parents + [node], child)), file=f)
+    print(
+        "DECODE_END_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))".format(
+            name, 2**width, lsb, width
+        ),
+        file=f,
+    )
     print(file=f)
     parents.append(node)
-    for child in node['children']:
+    for child in node["children"]:
         print_node(f, child, parents)
     parents.pop()
 
+
 def print_tree(f, tree):
     print_node(f, tree, [])
 
+
 def print_match_info(f):
     for tag in sorted(encs.keys(), key=iset.tags.index):
-        enc = ''.join(reversed(encs[tag]))
-        mask = int(re.sub(r'[^1]', r'0', enc.replace('0', '1')), 2)
-        match = int(re.sub(r'[^01]', r'0', enc), 2)
-        suffix = ''
-        print('DECODE{}_MATCH_INFO({},0x{:x}U,0x{:x}U)'.\
-            format(suffix, tag, mask, match), file=f)
+        enc = "".join(reversed(encs[tag]))
+        mask = int(re.sub(r"[^1]", r"0", enc.replace("0", "1")), 2)
+        match = int(re.sub(r"[^01]", r"0", enc), 2)
+        suffix = ""
+        print(
+            "DECODE{}_MATCH_INFO({},0x{:x}U,0x{:x}U)".format(suffix, tag, mask, match),
+            file=f,
+        )
+
+
+regre = re.compile(r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
+immre = re.compile(r"[#]([rRsSuUm])(\d+)(?:[:](\d+))?")
 
-regre = re.compile(
-    r'((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)')
-immre = re.compile(r'[#]([rRsSuUm])(\d+)(?:[:](\d+))?')
 
 def ordered_unique(l):
     return sorted(set(l), key=l.index)
 
-implicit_registers = {
-    'SP' : 29,
-    'FP' : 30,
-    'LR' : 31
-}
 
-num_registers = {
-    'R' : 32,
-    'V' : 32
-}
+implicit_registers = {"SP": 29, "FP": 30, "LR": 31}
+
+num_registers = {"R": 32, "V": 32}
+
 
 def print_op_info(f):
     for tag in sorted(encs.keys(), key=iset.tags.index):
         enc = encs[tag]
         print(file=f)
-        print('DECODE_OPINFO({},'.format(tag), file=f)
-        regs = ordered_unique(regre.findall(iset.iset[tag]['syntax']))
-        imms = ordered_unique(immre.findall(iset.iset[tag]['syntax']))
+        print("DECODE_OPINFO({},".format(tag), file=f)
+        regs = ordered_unique(regre.findall(iset.iset[tag]["syntax"]))
+        imms = ordered_unique(immre.findall(iset.iset[tag]["syntax"]))
         regno = 0
         for reg in regs:
             reg_type = reg[0]
             reg_letter = reg[1][0]
-            reg_num_choices = int(reg[3].rstrip('S'))
-            reg_mapping = reg[0] + ''.join(['_' for letter in reg[1]]) + reg[3]
-            reg_enc_fields = re.findall(reg_letter + '+', enc)
+            reg_num_choices = int(reg[3].rstrip("S"))
+            reg_mapping = reg[0] + "".join(["_" for letter in reg[1]]) + reg[3]
+            reg_enc_fields = re.findall(reg_letter + "+", enc)
             if len(reg_enc_fields) == 0:
                 raise Exception('Tag "{}" missing register field!'.format(tag))
             if len(reg_enc_fields) > 1:
-                raise Exception('Tag "{}" has split register field!'.\
-                    format(tag))
+                raise Exception('Tag "{}" has split register field!'.format(tag))
             reg_enc_field = reg_enc_fields[0]
             if 2 ** len(reg_enc_field) != reg_num_choices:
-                raise Exception('Tag "{}" has incorrect register field width!'.\
-                    format(tag))
-            print('        DECODE_REG({},{},{})'.\
-                format(regno, len(reg_enc_field), enc.index(reg_enc_field)),
-                       file=f)
-            if reg_type in num_registers and \
-                reg_num_choices != num_registers[reg_type]:
-                print('        DECODE_MAPPED_REG({},{})'.\
-                    format(regno, reg_mapping), file=f)
+                raise Exception(
+                    'Tag "{}" has incorrect register field width!'.format(tag)
+                )
+            print(
+                "        DECODE_REG({},{},{})".format(
+                    regno, len(reg_enc_field), enc.index(reg_enc_field)
+                ),
+                file=f,
+            )
+            if reg_type in num_registers and reg_num_choices != num_registers[reg_type]:
+                print(
+                    "        DECODE_MAPPED_REG({},{})".format(regno, reg_mapping),
+                    file=f,
+                )
             regno += 1
+
         def implicit_register_key(reg):
             return implicit_registers[reg]
+
         for reg in sorted(
-            set([r for r in (iset.iset[tag]['rregs'].split(',') + \
-                iset.iset[tag]['wregs'].split(',')) \
-                    if r in implicit_registers]), key=implicit_register_key):
-            print('        DECODE_IMPL_REG({},{})'.\
-                format(regno, implicit_registers[reg]), file=f)
+            set(
+                [
+                    r
+                    for r in (
+                        iset.iset[tag]["rregs"].split(",")
+                        + iset.iset[tag]["wregs"].split(",")
+                    )
+                    if r in implicit_registers
+                ]
+            ),
+            key=implicit_register_key,
+        ):
+            print(
+                "        DECODE_IMPL_REG({},{})".format(regno, implicit_registers[reg]),
+                file=f,
+            )
             regno += 1
         if imms and imms[0][0].isupper():
             imms = reversed(imms)
@@ -311,41 +359,45 @@ def print_op_info(f):
             else:
                 imm_shift = 0
             if imm_type.islower():
-                imm_letter = 'i'
+                imm_letter = "i"
             else:
-                imm_letter = 'I'
+                imm_letter = "I"
             remainder = imm_width
-            for m in reversed(list(re.finditer(imm_letter + '+', enc))):
+            for m in reversed(list(re.finditer(imm_letter + "+", enc))):
                 remainder -= m.end() - m.start()
-                print('        DECODE_IMM({},{},{},{})'.\
-                    format(immno, m.end() - m.start(), m.start(), remainder),
-                        file=f)
+                print(
+                    "        DECODE_IMM({},{},{},{})".format(
+                        immno, m.end() - m.start(), m.start(), remainder
+                    ),
+                    file=f,
+                )
             if remainder != 0:
                 if imm[2]:
-                    imm[2] = ':' + imm[2]
-                raise Exception('Tag "{}" has an incorrect number of ' + \
-                    'encoding bits for immediate "{}"'.\
-                    format(tag, ''.join(imm)))
-            if imm_type.lower() in 'sr':
-                print('        DECODE_IMM_SXT({},{})'.\
-                    format(immno, imm_width), file=f)
-            if imm_type.lower() == 'n':
-                print('        DECODE_IMM_NEG({},{})'.\
-                    format(immno, imm_width), file=f)
+                    imm[2] = ":" + imm[2]
+                raise Exception(
+                    'Tag "{}" has an incorrect number of '
+                    + 'encoding bits for immediate "{}"'.format(tag, "".join(imm))
+                )
+            if imm_type.lower() in "sr":
+                print("        DECODE_IMM_SXT({},{})".format(immno, imm_width), file=f)
+            if imm_type.lower() == "n":
+                print("        DECODE_IMM_NEG({},{})".format(immno, imm_width), file=f)
             if imm_shift:
-                print('        DECODE_IMM_SHIFT({},{})'.\
-                    format(immno, imm_shift), file=f)
-        print(')', file=f)
+                print(
+                    "        DECODE_IMM_SHIFT({},{})".format(immno, imm_shift), file=f
+                )
+        print(")", file=f)
+
 
-if __name__ == '__main__':
-    with open(sys.argv[1], 'w') as f:
+if __name__ == "__main__":
+    with open(sys.argv[1], "w") as f:
         print_tree(f, dectree_normal)
         print_tree(f, dectree_16bit)
         if subinsn_groupings:
             print_tree(f, dectree_subinsn_groupings)
-        for (name, dectree_subinsn) in sorted(dectree_subinsns.items()):
+        for name, dectree_subinsn in sorted(dectree_subinsns.items()):
             print_tree(f, dectree_subinsn)
-        for (name, dectree_ext) in sorted(dectree_extensions.items()):
+        for name, dectree_ext in sorted(dectree_extensions.items()):
             print_tree(f, dectree_ext)
         print_match_info(f)
         print_op_info(f)
diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py
index ebd3e7a..c74443d 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -22,162 +22,141 @@ import re
 import string
 import hex_common
 
+
 ##
 ## Helpers for gen_analyze_func
 ##
 def is_predicated(tag):
-    return 'A_CONDEXEC' in hex_common.attribdict[tag]
+    return "A_CONDEXEC" in hex_common.attribdict[tag]
+
 
 def analyze_opn_old(f, tag, regtype, regid, regno):
-    regN = "%s%sN" % (regtype, regid)
+    regN = f"{regtype}{regid}N"
     predicated = "true" if is_predicated(tag) else "false"
-    if (regtype == "R"):
-        if (regid in {"ss", "tt"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"dd", "ee", "xx", "yy"}):
-            f.write("    const int %s = insn->regno[%d];\n" % (regN, regno))
-            f.write("    ctx_log_reg_write_pair(ctx, %s, %s);\n" % \
-                (regN, predicated))
-        elif (regid in {"s", "t", "u", "v"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"d", "e", "x", "y"}):
-            f.write("    const int %s = insn->regno[%d];\n" % (regN, regno))
-            f.write("    ctx_log_reg_write(ctx, %s, %s);\n" % \
-                (regN, predicated))
+    if regtype == "R":
+        if regid in {"ss", "tt"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"dd", "ee", "xx", "yy"}:
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+            f.write(f"    ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
+        elif regid in {"s", "t", "u", "v"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"d", "e", "x", "y"}:
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+            f.write(f"    ctx_log_reg_write(ctx, {regN}, {predicated});\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid in {"s", "t", "u", "v"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"d", "e", "x"}):
-            f.write("    const int %s = insn->regno[%d];\n" % (regN, regno))
-            f.write("    ctx_log_pred_write(ctx, %s);\n" % (regN))
+    elif regtype == "P":
+        if regid in {"s", "t", "u", "v"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"d", "e", "x"}:
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+            f.write(f"    ctx_log_pred_write(ctx, {regN});\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "C"):
-        if (regid == "ss"):
-            f.write("//    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-                (regN, regno))
-        elif (regid == "dd"):
-            f.write("    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-                (regN, regno))
-            f.write("    ctx_log_reg_write_pair(ctx, %s, %s);\n" % \
-                (regN, predicated))
-        elif (regid == "s"):
-            f.write("//    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-                (regN, regno))
-        elif (regid == "d"):
-            f.write("    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-                (regN, regno))
-            f.write("    ctx_log_reg_write(ctx, %s, %s);\n" % \
-                (regN, predicated))
+    elif regtype == "C":
+        if regid == "ss":
+            f.write(
+                f"//    const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
+            )
+        elif regid == "dd":
+            f.write(f"    const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
+            f.write(f"    ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
+        elif regid == "s":
+            f.write(
+                f"//    const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n"
+            )
+        elif regid == "d":
+            f.write(f"    const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
+            f.write(f"    ctx_log_reg_write(ctx, {regN}, {predicated});\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "M"):
-        if (regid == "u"):
-            f.write("//    const int %s = insn->regno[%d];\n"% \
-                (regN, regno))
+    elif regtype == "M":
+        if regid == "u":
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "V"):
+    elif regtype == "V":
         newv = "EXT_DFL"
-        if (hex_common.is_new_result(tag)):
+        if hex_common.is_new_result(tag):
             newv = "EXT_NEW"
-        elif (hex_common.is_tmp_result(tag)):
+        elif hex_common.is_tmp_result(tag):
             newv = "EXT_TMP"
-        if (regid in {"dd", "xx"}):
-            f.write("    const int %s = insn->regno[%d];\n" %\
-                (regN, regno))
-            f.write("    ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
-                (regN, newv, predicated))
-        elif (regid in {"uu", "vv"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"s", "u", "v", "w"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"d", "x", "y"}):
-            f.write("    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-            f.write("    ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
-                (regN, newv, predicated))
+        if regid in {"dd", "xx"}:
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+            f.write(
+                f"    ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n"
+            )
+        elif regid in {"uu", "vv"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"s", "u", "v", "w"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"d", "x", "y"}:
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+            f.write(f"    ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "Q"):
-        if (regid in {"d", "e", "x"}):
-            f.write("    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-            f.write("    ctx_log_qreg_write(ctx, %s);\n" % (regN))
-        elif (regid in {"s", "t", "u", "v"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
+    elif regtype == "Q":
+        if regid in {"d", "e", "x"}:
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+            f.write(f"    ctx_log_qreg_write(ctx, {regN});\n")
+        elif regid in {"s", "t", "u", "v"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "G"):
-        if (regid in {"dd"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"d"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"ss"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"s"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
+    elif regtype == "G":
+        if regid in {"dd"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"d"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"ss"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"s"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "S"):
-        if (regid in {"dd"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"d"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"ss"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"s"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
+    elif regtype == "S":
+        if regid in {"dd"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"d"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"ss"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"s"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
+
 def analyze_opn_new(f, tag, regtype, regid, regno):
-    regN = "%s%sN" % (regtype, regid)
-    if (regtype == "N"):
-        if (regid in {"s", "t"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
+    regN = f"{regtype}{regid}N"
+    if regtype == "N":
+        if regid in {"s", "t"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid in {"t", "u", "v"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
+    elif regtype == "P":
+        if regid in {"t", "u", "v"}:
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "O"):
-        if (regid == "s"):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
+    elif regtype == "O":
+        if regid == "s":
+            f.write(f"//    const int {regN} = insn->regno[{regno}];\n")
         else:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
+
 def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
-    if (hex_common.is_pair(regid)):
+    if hex_common.is_pair(regid):
         analyze_opn_old(f, tag, regtype, regid, i)
-    elif (hex_common.is_single(regid)):
+    elif hex_common.is_single(regid):
         if hex_common.is_old_val(regtype, regid, tag):
-            analyze_opn_old(f,tag, regtype, regid, i)
+            analyze_opn_old(f, tag, regtype, regid, i)
         elif hex_common.is_new_val(regtype, regid, tag):
             analyze_opn_new(f, tag, regtype, regid, i)
         else:
@@ -185,6 +164,7 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
     else:
         print("Bad register parse: ", regtype, regid, toss, numregs)
 
+
 ##
 ## Generate the code to analyze the instruction
 ##     For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
@@ -199,25 +179,26 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
 ##     }
 ##
 def gen_analyze_func(f, tag, regs, imms):
-    f.write("static void analyze_%s(DisasContext *ctx)\n" %tag)
-    f.write('{\n')
+    f.write(f"static void analyze_{tag}(DisasContext *ctx)\n")
+    f.write("{\n")
 
     f.write("    Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
 
-    i=0
+    i = 0
     ## Analyze all the registers
     for regtype, regid, toss, numregs in regs:
         analyze_opn(f, tag, regtype, regid, toss, numregs, i)
         i += 1
 
-    has_generated_helper = (not hex_common.skip_qemu_helper(tag) and
-                            not hex_common.is_idef_parser_enabled(tag))
-    if (has_generated_helper and
-        'A_SCALAR_LOAD' in hex_common.attribdict[tag]):
+    has_generated_helper = not hex_common.skip_qemu_helper(
+        tag
+    ) and not hex_common.is_idef_parser_enabled(tag)
+    if has_generated_helper and "A_SCALAR_LOAD" in hex_common.attribdict[tag]:
         f.write("    ctx->need_pkt_has_store_s1 = true;\n")
 
     f.write("}\n\n")
 
+
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
@@ -239,7 +220,7 @@ def main():
     tagregs = hex_common.get_tagregs()
     tagimms = hex_common.get_tagimms()
 
-    with open(sys.argv[-1], 'w') as f:
+    with open(sys.argv[-1], "w") as f:
         f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
         f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
 
@@ -248,5 +229,6 @@ def main():
 
         f.write("#endif    /* HEXAGON_TCG_FUNCS_H */\n")
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper_funcs.py
index 7a224b6..c73d792 100755
--- a/target/hexagon/gen_helper_funcs.py
+++ b/target/hexagon/gen_helper_funcs.py
@@ -22,133 +22,171 @@ import re
 import string
 import hex_common
 
+
 ##
 ## Helpers for gen_helper_function
 ##
 def gen_decl_ea(f):
     f.write("    uint32_t EA;\n")
 
-def gen_helper_return_type(f,regtype,regid,regno):
-    if regno > 1 : f.write(", ")
+
+def gen_helper_return_type(f, regtype, regid, regno):
+    if regno > 1:
+        f.write(", ")
     f.write("int32_t")
 
-def gen_helper_return_type_pair(f,regtype,regid,regno):
-    if regno > 1 : f.write(", ")
+
+def gen_helper_return_type_pair(f, regtype, regid, regno):
+    if regno > 1:
+        f.write(", ")
     f.write("int64_t")
 
-def gen_helper_arg(f,regtype,regid,regno):
-    if regno > 0 : f.write(", " )
-    f.write("int32_t %s%sV" % (regtype,regid))
 
-def gen_helper_arg_new(f,regtype,regid,regno):
-    if regno >= 0 : f.write(", " )
-    f.write("int32_t %s%sN" % (regtype,regid))
+def gen_helper_arg(f, regtype, regid, regno):
+    if regno > 0:
+        f.write(", ")
+    f.write(f"int32_t {regtype}{regid}V")
+
+
+def gen_helper_arg_new(f, regtype, regid, regno):
+    if regno >= 0:
+        f.write(", ")
+    f.write(f"int32_t {regtype}{regid}N")
+
+
+def gen_helper_arg_pair(f, regtype, regid, regno):
+    if regno >= 0:
+        f.write(", ")
+    f.write(f"int64_t {regtype}{regid}V")
 
-def gen_helper_arg_pair(f,regtype,regid,regno):
-    if regno >= 0 : f.write(", ")
-    f.write("int64_t %s%sV" % (regtype,regid))
 
-def gen_helper_arg_ext(f,regtype,regid,regno):
-    if regno > 0 : f.write(", ")
-    f.write("void *%s%sV_void" % (regtype,regid))
+def gen_helper_arg_ext(f, regtype, regid, regno):
+    if regno > 0:
+        f.write(", ")
+    f.write(f"void *{regtype}{regid}V_void")
 
-def gen_helper_arg_ext_pair(f,regtype,regid,regno):
-    if regno > 0 : f.write(", ")
-    f.write("void *%s%sV_void" % (regtype,regid))
 
-def gen_helper_arg_opn(f,regtype,regid,i,tag):
-    if (hex_common.is_pair(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            gen_helper_arg_ext_pair(f,regtype,regid,i)
+def gen_helper_arg_ext_pair(f, regtype, regid, regno):
+    if regno > 0:
+        f.write(", ")
+    f.write(f"void *{regtype}{regid}V_void")
+
+
+def gen_helper_arg_opn(f, regtype, regid, i, tag):
+    if hex_common.is_pair(regid):
+        if hex_common.is_hvx_reg(regtype):
+            gen_helper_arg_ext_pair(f, regtype, regid, i)
         else:
-            gen_helper_arg_pair(f,regtype,regid,i)
-    elif (hex_common.is_single(regid)):
+            gen_helper_arg_pair(f, regtype, regid, i)
+    elif hex_common.is_single(regid):
         if hex_common.is_old_val(regtype, regid, tag):
-            if (hex_common.is_hvx_reg(regtype)):
-                gen_helper_arg_ext(f,regtype,regid,i)
+            if hex_common.is_hvx_reg(regtype):
+                gen_helper_arg_ext(f, regtype, regid, i)
             else:
-                gen_helper_arg(f,regtype,regid,i)
+                gen_helper_arg(f, regtype, regid, i)
         elif hex_common.is_new_val(regtype, regid, tag):
-            gen_helper_arg_new(f,regtype,regid,i)
+            gen_helper_arg_new(f, regtype, regid, i)
         else:
-            print("Bad register parse: ",regtype,regid,toss,numregs)
+            print("Bad register parse: ", regtype, regid, toss, numregs)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
+
+def gen_helper_arg_imm(f, immlett):
+    f.write(f", int32_t {hex_common.imm_name(immlett)}")
 
-def gen_helper_arg_imm(f,immlett):
-    f.write(", int32_t %s" % (hex_common.imm_name(immlett)))
 
-def gen_helper_dest_decl(f,regtype,regid,regno,subfield=""):
-    f.write("    int32_t %s%sV%s = 0;\n" % \
-        (regtype,regid,subfield))
+def gen_helper_dest_decl(f, regtype, regid, regno, subfield=""):
+    f.write(f"    int32_t {regtype}{regid}V{subfield} = 0;\n")
 
-def gen_helper_dest_decl_pair(f,regtype,regid,regno,subfield=""):
-    f.write("    int64_t %s%sV%s = 0;\n" % \
-        (regtype,regid,subfield))
 
-def gen_helper_dest_decl_ext(f,regtype,regid):
-    if (regtype == "Q"):
-        f.write("    /* %s%sV is *(MMQReg *)(%s%sV_void) */\n" % \
-            (regtype,regid,regtype,regid))
+def gen_helper_dest_decl_pair(f, regtype, regid, regno, subfield=""):
+    f.write(f"    int64_t {regtype}{regid}V{subfield} = 0;\n")
+
+
+def gen_helper_dest_decl_ext(f, regtype, regid):
+    if regtype == "Q":
+        f.write(
+            f"    /* {regtype}{regid}V is *(MMQReg *)" f"({regtype}{regid}V_void) */\n"
+        )
     else:
-        f.write("    /* %s%sV is *(MMVector *)(%s%sV_void) */\n" % \
-            (regtype,regid,regtype,regid))
+        f.write(
+            f"    /* {regtype}{regid}V is *(MMVector *)"
+            f"({regtype}{regid}V_void) */\n"
+        )
+
 
-def gen_helper_dest_decl_ext_pair(f,regtype,regid,regno):
-    f.write("    /* %s%sV is *(MMVectorPair *))%s%sV_void) */\n" % \
-        (regtype,regid,regtype, regid))
+def gen_helper_dest_decl_ext_pair(f, regtype, regid, regno):
+    f.write(
+        f"    /* {regtype}{regid}V is *(MMVectorPair *))"
+        f"{regtype}{regid}V_void) */\n"
+    )
 
-def gen_helper_dest_decl_opn(f,regtype,regid,i):
-    if (hex_common.is_pair(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            gen_helper_dest_decl_ext_pair(f,regtype,regid, i)
+
+def gen_helper_dest_decl_opn(f, regtype, regid, i):
+    if hex_common.is_pair(regid):
+        if hex_common.is_hvx_reg(regtype):
+            gen_helper_dest_decl_ext_pair(f, regtype, regid, i)
         else:
-            gen_helper_dest_decl_pair(f,regtype,regid,i)
-    elif (hex_common.is_single(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            gen_helper_dest_decl_ext(f,regtype,regid)
+            gen_helper_dest_decl_pair(f, regtype, regid, i)
+    elif hex_common.is_single(regid):
+        if hex_common.is_hvx_reg(regtype):
+            gen_helper_dest_decl_ext(f, regtype, regid)
         else:
-            gen_helper_dest_decl(f,regtype,regid,i)
+            gen_helper_dest_decl(f, regtype, regid, i)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
 
-def gen_helper_src_var_ext(f,regtype,regid):
-    if (regtype == "Q"):
-       f.write("    /* %s%sV is *(MMQReg *)(%s%sV_void) */\n" % \
-           (regtype,regid,regtype,regid))
+def gen_helper_src_var_ext(f, regtype, regid):
+    if regtype == "Q":
+        f.write(
+            f"    /* {regtype}{regid}V is *(MMQReg *)" f"({regtype}{regid}V_void) */\n"
+        )
     else:
-       f.write("    /* %s%sV is *(MMVector *)(%s%sV_void) */\n" % \
-           (regtype,regid,regtype,regid))
+        f.write(
+            f"    /* {regtype}{regid}V is *(MMVector *)"
+            f"({regtype}{regid}V_void) */\n"
+        )
+
+
+def gen_helper_src_var_ext_pair(f, regtype, regid, regno):
+    f.write(
+        f"    /* {regtype}{regid}V{regno} is *(MMVectorPair *)"
+        f"({regtype}{regid}V{regno}_void) */\n"
+    )
 
-def gen_helper_src_var_ext_pair(f,regtype,regid,regno):
-    f.write("    /* %s%sV%s is *(MMVectorPair *)(%s%sV%s_void) */\n" % \
-        (regtype,regid,regno,regtype,regid,regno))
 
-def gen_helper_return(f,regtype,regid,regno):
-    f.write("    return %s%sV;\n" % (regtype,regid))
+def gen_helper_return(f, regtype, regid, regno):
+    f.write(f"    return {regtype}{regid}V;\n")
 
-def gen_helper_return_pair(f,regtype,regid,regno):
-    f.write("    return %s%sV;\n" % (regtype,regid))
 
-def gen_helper_dst_write_ext(f,regtype,regid):
+def gen_helper_return_pair(f, regtype, regid, regno):
+    f.write(f"    return {regtype}{regid}V;\n")
+
+
+def gen_helper_dst_write_ext(f, regtype, regid):
     return
 
-def gen_helper_dst_write_ext_pair(f,regtype,regid):
+
+def gen_helper_dst_write_ext_pair(f, regtype, regid):
     return
 
+
 def gen_helper_return_opn(f, regtype, regid, i):
-    if (hex_common.is_pair(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            gen_helper_dst_write_ext_pair(f,regtype,regid)
+    if hex_common.is_pair(regid):
+        if hex_common.is_hvx_reg(regtype):
+            gen_helper_dst_write_ext_pair(f, regtype, regid)
         else:
-            gen_helper_return_pair(f,regtype,regid,i)
-    elif (hex_common.is_single(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            gen_helper_dst_write_ext(f,regtype,regid)
+            gen_helper_return_pair(f, regtype, regid, i)
+    elif hex_common.is_single(regid):
+        if hex_common.is_hvx_reg(regtype):
+            gen_helper_dst_write_ext(f, regtype, regid)
         else:
-            gen_helper_return(f,regtype,regid,i)
+            gen_helper_return(f, regtype, regid, i)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
 
 ##
 ## Generate the TCG code to call the helper
@@ -170,138 +208,143 @@ def gen_helper_function(f, tag, tagregs, tagimms):
     numresults = 0
     numscalarresults = 0
     numscalarreadwrite = 0
-    for regtype,regid,toss,numregs in regs:
-        if (hex_common.is_written(regid)):
+    for regtype, regid, toss, numregs in regs:
+        if hex_common.is_written(regid):
             numresults += 1
-            if (hex_common.is_scalar_reg(regtype)):
+            if hex_common.is_scalar_reg(regtype):
                 numscalarresults += 1
-        if (hex_common.is_readwrite(regid)):
-            if (hex_common.is_scalar_reg(regtype)):
+        if hex_common.is_readwrite(regid):
+            if hex_common.is_scalar_reg(regtype):
                 numscalarreadwrite += 1
 
-    if (numscalarresults > 1):
+    if numscalarresults > 1:
         ## The helper is bogus when there is more than one result
-        f.write("void HELPER(%s)(CPUHexagonState *env) { BOGUS_HELPER(%s); }\n"
-                % (tag, tag))
+        f.write(
+            f"void HELPER({tag})(CPUHexagonState *env) " f"{{ BOGUS_HELPER({tag}); }}\n"
+        )
     else:
         ## The return type of the function is the type of the destination
         ## register (if scalar)
-        i=0
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
-                if (hex_common.is_pair(regid)):
-                    if (hex_common.is_hvx_reg(regtype)):
+        i = 0
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
+                if hex_common.is_pair(regid):
+                    if hex_common.is_hvx_reg(regtype):
                         continue
                     else:
-                        gen_helper_return_type_pair(f,regtype,regid,i)
-                elif (hex_common.is_single(regid)):
-                    if (hex_common.is_hvx_reg(regtype)):
-                            continue
+                        gen_helper_return_type_pair(f, regtype, regid, i)
+                elif hex_common.is_single(regid):
+                    if hex_common.is_hvx_reg(regtype):
+                        continue
                     else:
-                        gen_helper_return_type(f,regtype,regid,i)
+                        gen_helper_return_type(f, regtype, regid, i)
                 else:
-                    print("Bad register parse: ",regtype,regid,toss,numregs)
+                    print("Bad register parse: ", regtype, regid, toss, numregs)
             i += 1
 
-        if (numscalarresults == 0):
+        if numscalarresults == 0:
             f.write("void")
-        f.write(" HELPER(%s)(CPUHexagonState *env" % tag)
+        f.write(f" HELPER({tag})(CPUHexagonState *env")
 
         ## Arguments include the vector destination operands
         i = 1
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
-                if (hex_common.is_pair(regid)):
-                    if (hex_common.is_hvx_reg(regtype)):
-                        gen_helper_arg_ext_pair(f,regtype,regid,i)
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
+                if hex_common.is_pair(regid):
+                    if hex_common.is_hvx_reg(regtype):
+                        gen_helper_arg_ext_pair(f, regtype, regid, i)
                     else:
                         continue
-                elif (hex_common.is_single(regid)):
-                    if (hex_common.is_hvx_reg(regtype)):
-                        gen_helper_arg_ext(f,regtype,regid,i)
+                elif hex_common.is_single(regid):
+                    if hex_common.is_hvx_reg(regtype):
+                        gen_helper_arg_ext(f, regtype, regid, i)
                     else:
                         # This is the return value of the function
                         continue
                 else:
-                    print("Bad register parse: ",regtype,regid,toss,numregs)
+                    print("Bad register parse: ", regtype, regid, toss, numregs)
                 i += 1
 
         ## For conditional instructions, we pass in the destination register
-        if 'A_CONDEXEC' in hex_common.attribdict[tag]:
+        if "A_CONDEXEC" in hex_common.attribdict[tag]:
             for regtype, regid, toss, numregs in regs:
-                if (hex_common.is_writeonly(regid) and
-                    not hex_common.is_hvx_reg(regtype)):
+                if hex_common.is_writeonly(regid) and not hex_common.is_hvx_reg(
+                    regtype
+                ):
                     gen_helper_arg_opn(f, regtype, regid, i, tag)
                     i += 1
 
         ## Arguments to the helper function are the source regs and immediates
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_read(regid)):
-                if (hex_common.is_hvx_reg(regtype) and
-                    hex_common.is_readwrite(regid)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_read(regid):
+                if hex_common.is_hvx_reg(regtype) and hex_common.is_readwrite(regid):
                     continue
-                gen_helper_arg_opn(f,regtype,regid,i,tag)
+                gen_helper_arg_opn(f, regtype, regid, i, tag)
                 i += 1
-        for immlett,bits,immshift in imms:
-            gen_helper_arg_imm(f,immlett)
+        for immlett, bits, immshift in imms:
+            gen_helper_arg_imm(f, immlett)
             i += 1
 
-        if (hex_common.need_pkt_has_multi_cof(tag)):
+        if hex_common.need_pkt_has_multi_cof(tag):
             f.write(", uint32_t pkt_has_multi_cof")
 
         if hex_common.need_PC(tag):
-            if i > 0: f.write(", ")
+            if i > 0:
+                f.write(", ")
             f.write("target_ulong PC")
             i += 1
         if hex_common.helper_needs_next_PC(tag):
-            if i > 0: f.write(", ")
+            if i > 0:
+                f.write(", ")
             f.write("target_ulong next_PC")
             i += 1
         if hex_common.need_slot(tag):
-            if i > 0: f.write(", ")
+            if i > 0:
+                f.write(", ")
             f.write("uint32_t slot")
             i += 1
         if hex_common.need_part1(tag):
-            if i > 0: f.write(", ")
+            if i > 0:
+                f.write(", ")
             f.write("uint32_t part1")
         f.write(")\n{\n")
-        if (not hex_common.need_slot(tag)):
-            f.write("    uint32_t slot __attribute__((unused)) = 4;\n" )
-        if hex_common.need_ea(tag): gen_decl_ea(f)
+        if hex_common.need_ea(tag):
+            gen_decl_ea(f)
         ## Declare the return variable
-        i=0
-        if 'A_CONDEXEC' not in hex_common.attribdict[tag]:
-            for regtype,regid,toss,numregs in regs:
-                if (hex_common.is_writeonly(regid)):
-                    gen_helper_dest_decl_opn(f,regtype,regid,i)
+        i = 0
+        if "A_CONDEXEC" not in hex_common.attribdict[tag]:
+            for regtype, regid, toss, numregs in regs:
+                if hex_common.is_writeonly(regid):
+                    gen_helper_dest_decl_opn(f, regtype, regid, i)
                 i += 1
 
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_read(regid)):
-                if (hex_common.is_pair(regid)):
-                    if (hex_common.is_hvx_reg(regtype)):
-                        gen_helper_src_var_ext_pair(f,regtype,regid,i)
-                elif (hex_common.is_single(regid)):
-                    if (hex_common.is_hvx_reg(regtype)):
-                        gen_helper_src_var_ext(f,regtype,regid)
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_read(regid):
+                if hex_common.is_pair(regid):
+                    if hex_common.is_hvx_reg(regtype):
+                        gen_helper_src_var_ext_pair(f, regtype, regid, i)
+                elif hex_common.is_single(regid):
+                    if hex_common.is_hvx_reg(regtype):
+                        gen_helper_src_var_ext(f, regtype, regid)
                 else:
-                    print("Bad register parse: ",regtype,regid,toss,numregs)
+                    print("Bad register parse: ", regtype, regid, toss, numregs)
 
-        if 'A_FPOP' in hex_common.attribdict[tag]:
-            f.write('    arch_fpop_start(env);\n');
+        if "A_FPOP" in hex_common.attribdict[tag]:
+            f.write("    arch_fpop_start(env);\n")
 
-        f.write("    %s\n" % hex_common.semdict[tag])
+        f.write(f"    {hex_common.semdict[tag]}\n")
 
-        if 'A_FPOP' in hex_common.attribdict[tag]:
-            f.write('    arch_fpop_end(env);\n');
+        if "A_FPOP" in hex_common.attribdict[tag]:
+            f.write("    arch_fpop_end(env);\n")
 
         ## Save/return the return variable
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
                 gen_helper_return_opn(f, regtype, regid, i)
         f.write("}\n\n")
         ## End of the helper definition
 
+
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
@@ -324,27 +367,28 @@ def main():
     tagimms = hex_common.get_tagimms()
 
     output_file = sys.argv[-1]
-    with open(output_file, 'w') as f:
+    with open(output_file, "w") as f:
         for tag in hex_common.tags:
             ## Skip the priv instructions
-            if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+            if "A_PRIV" in hex_common.attribdict[tag]:
                 continue
             ## Skip the guest instructions
-            if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+            if "A_GUEST" in hex_common.attribdict[tag]:
                 continue
             ## Skip the diag instructions
-            if ( tag == "Y6_diag" ) :
+            if tag == "Y6_diag":
                 continue
-            if ( tag == "Y6_diag0" ) :
+            if tag == "Y6_diag0":
                 continue
-            if ( tag == "Y6_diag1" ) :
+            if tag == "Y6_diag1":
                 continue
-            if ( hex_common.skip_qemu_helper(tag) ):
+            if hex_common.skip_qemu_helper(tag):
                 continue
-            if ( hex_common.is_idef_parser_enabled(tag) ):
+            if hex_common.is_idef_parser_enabled(tag):
                 continue
 
             gen_helper_function(f, tag, tagregs, tagimms)
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helper_protos.py
index ddddc9e..187cd6e 100755
--- a/target/hexagon/gen_helper_protos.py
+++ b/target/hexagon/gen_helper_protos.py
@@ -26,32 +26,34 @@ import hex_common
 ## Helpers for gen_helper_prototype
 ##
 def_helper_types = {
-    'N' : 's32',
-    'O' : 's32',
-    'P' : 's32',
-    'M' : 's32',
-    'C' : 's32',
-    'R' : 's32',
-    'V' : 'ptr',
-    'Q' : 'ptr'
+    "N": "s32",
+    "O": "s32",
+    "P": "s32",
+    "M": "s32",
+    "C": "s32",
+    "R": "s32",
+    "V": "ptr",
+    "Q": "ptr",
 }
 
 def_helper_types_pair = {
-    'R' : 's64',
-    'C' : 's64',
-    'S' : 's64',
-    'G' : 's64',
-    'V' : 'ptr',
-    'Q' : 'ptr'
+    "R": "s64",
+    "C": "s64",
+    "S": "s64",
+    "G": "s64",
+    "V": "ptr",
+    "Q": "ptr",
 }
 
+
 def gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i):
-    if (hex_common.is_pair(regid)):
-        f.write(", %s" % (def_helper_types_pair[regtype]))
-    elif (hex_common.is_single(regid)):
-        f.write(", %s" % (def_helper_types[regtype]))
+    if hex_common.is_pair(regid):
+        f.write(f", {def_helper_types_pair[regtype]}")
+    elif hex_common.is_single(regid):
+        f.write(f", {def_helper_types[regtype]}")
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
 
 ##
 ## Generate the DEF_HELPER prototype for an instruction
@@ -66,90 +68,108 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
     numresults = 0
     numscalarresults = 0
     numscalarreadwrite = 0
-    for regtype,regid,toss,numregs in regs:
-        if (hex_common.is_written(regid)):
+    for regtype, regid, toss, numregs in regs:
+        if hex_common.is_written(regid):
             numresults += 1
-            if (hex_common.is_scalar_reg(regtype)):
+            if hex_common.is_scalar_reg(regtype):
                 numscalarresults += 1
-        if (hex_common.is_readwrite(regid)):
-            if (hex_common.is_scalar_reg(regtype)):
+        if hex_common.is_readwrite(regid):
+            if hex_common.is_scalar_reg(regtype):
                 numscalarreadwrite += 1
 
-    if (numscalarresults > 1):
+    if numscalarresults > 1:
         ## The helper is bogus when there is more than one result
-        f.write('DEF_HELPER_1(%s, void, env)\n' % tag)
+        f.write(f"DEF_HELPER_1({tag}, void, env)\n")
     else:
         ## Figure out how many arguments the helper will take
-        if (numscalarresults == 0):
-            def_helper_size = len(regs)+len(imms)+numscalarreadwrite+1
-            if hex_common.need_pkt_has_multi_cof(tag): def_helper_size += 1
-            if hex_common.need_part1(tag): def_helper_size += 1
-            if hex_common.need_slot(tag): def_helper_size += 1
-            if hex_common.need_PC(tag): def_helper_size += 1
-            if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
-            if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
-            f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
+        if numscalarresults == 0:
+            def_helper_size = len(regs) + len(imms) + numscalarreadwrite + 1
+            if hex_common.need_pkt_has_multi_cof(tag):
+                def_helper_size += 1
+            if hex_common.need_part1(tag):
+                def_helper_size += 1
+            if hex_common.need_slot(tag):
+                def_helper_size += 1
+            if hex_common.need_PC(tag):
+                def_helper_size += 1
+            if hex_common.helper_needs_next_PC(tag):
+                def_helper_size += 1
+            if hex_common.need_condexec_reg(tag, regs):
+                def_helper_size += 1
+            f.write(f"DEF_HELPER_{def_helper_size}({tag}")
             ## The return type is void
-            f.write(', void' )
+            f.write(", void")
         else:
-            def_helper_size = len(regs)+len(imms)+numscalarreadwrite
-            if hex_common.need_pkt_has_multi_cof(tag): def_helper_size += 1
-            if hex_common.need_part1(tag): def_helper_size += 1
-            if hex_common.need_slot(tag): def_helper_size += 1
-            if hex_common.need_PC(tag): def_helper_size += 1
-            if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
-            if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
-            f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
+            def_helper_size = len(regs) + len(imms) + numscalarreadwrite
+            if hex_common.need_pkt_has_multi_cof(tag):
+                def_helper_size += 1
+            if hex_common.need_part1(tag):
+                def_helper_size += 1
+            if hex_common.need_slot(tag):
+                def_helper_size += 1
+            if hex_common.need_PC(tag):
+                def_helper_size += 1
+            if hex_common.need_condexec_reg(tag, regs):
+                def_helper_size += 1
+            if hex_common.helper_needs_next_PC(tag):
+                def_helper_size += 1
+            f.write(f"DEF_HELPER_{def_helper_size}({tag}")
 
         ## Generate the qemu DEF_HELPER type for each result
         ## Iterate over this list twice
         ## - Emit the scalar result
         ## - Emit the vector result
-        i=0
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
-                if (not hex_common.is_hvx_reg(regtype)):
+        i = 0
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
+                if not hex_common.is_hvx_reg(regtype):
                     gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
                 i += 1
 
         ## Put the env between the outputs and inputs
-        f.write(', env' )
+        f.write(", env")
         i += 1
 
         # Second pass
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
-                if (hex_common.is_hvx_reg(regtype)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
+                if hex_common.is_hvx_reg(regtype):
                     gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
                     i += 1
 
         ## For conditional instructions, we pass in the destination register
-        if 'A_CONDEXEC' in hex_common.attribdict[tag]:
+        if "A_CONDEXEC" in hex_common.attribdict[tag]:
             for regtype, regid, toss, numregs in regs:
-                if (hex_common.is_writeonly(regid) and
-                    not hex_common.is_hvx_reg(regtype)):
+                if hex_common.is_writeonly(regid) and not hex_common.is_hvx_reg(
+                    regtype
+                ):
                     gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
                     i += 1
 
         ## Generate the qemu type for each input operand (regs and immediates)
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_read(regid)):
-                if (hex_common.is_hvx_reg(regtype) and
-                    hex_common.is_readwrite(regid)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_read(regid):
+                if hex_common.is_hvx_reg(regtype) and hex_common.is_readwrite(regid):
                     continue
                 gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
                 i += 1
-        for immlett,bits,immshift in imms:
+        for immlett, bits, immshift in imms:
             f.write(", s32")
 
         ## Add the arguments for the instruction pkt_has_multi_cof, slot and
         ## part1 (if needed)
-        if hex_common.need_pkt_has_multi_cof(tag): f.write(', i32')
-        if hex_common.need_PC(tag): f.write(', i32')
-        if hex_common.helper_needs_next_PC(tag): f.write(', i32')
-        if hex_common.need_slot(tag): f.write(', i32' )
-        if hex_common.need_part1(tag): f.write(' , i32' )
-        f.write(')\n')
+        if hex_common.need_pkt_has_multi_cof(tag):
+            f.write(", i32")
+        if hex_common.need_PC(tag):
+            f.write(", i32")
+        if hex_common.helper_needs_next_PC(tag):
+            f.write(", i32")
+        if hex_common.need_slot(tag):
+            f.write(", i32")
+        if hex_common.need_part1(tag):
+            f.write(" , i32")
+        f.write(")\n")
+
 
 def main():
     hex_common.read_semantics_file(sys.argv[1])
@@ -173,28 +193,29 @@ def main():
     tagimms = hex_common.get_tagimms()
 
     output_file = sys.argv[-1]
-    with open(output_file, 'w') as f:
+    with open(output_file, "w") as f:
         for tag in hex_common.tags:
             ## Skip the priv instructions
-            if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+            if "A_PRIV" in hex_common.attribdict[tag]:
                 continue
             ## Skip the guest instructions
-            if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+            if "A_GUEST" in hex_common.attribdict[tag]:
                 continue
             ## Skip the diag instructions
-            if ( tag == "Y6_diag" ) :
+            if tag == "Y6_diag":
                 continue
-            if ( tag == "Y6_diag0" ) :
+            if tag == "Y6_diag0":
                 continue
-            if ( tag == "Y6_diag1" ) :
+            if tag == "Y6_diag1":
                 continue
 
-            if ( hex_common.skip_qemu_helper(tag) ):
+            if hex_common.skip_qemu_helper(tag):
                 continue
-            if ( hex_common.is_idef_parser_enabled(tag) ):
+            if hex_common.is_idef_parser_enabled(tag):
                 continue
 
             gen_helper_prototype(f, tag, tagregs, tagimms)
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py
index 917753d..afe68bd 100644
--- a/target/hexagon/gen_idef_parser_funcs.py
+++ b/target/hexagon/gen_idef_parser_funcs.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
+##  Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -24,6 +24,7 @@ from io import StringIO
 
 import hex_common
 
+
 ##
 ## Generate code to be fed to the idef_parser
 ##
@@ -48,83 +49,99 @@ def main():
     tagregs = hex_common.get_tagregs()
     tagimms = hex_common.get_tagimms()
 
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         f.write('#include "macros.inc"\n\n')
 
         for tag in hex_common.tags:
             ## Skip the priv instructions
-            if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+            if "A_PRIV" in hex_common.attribdict[tag]:
                 continue
             ## Skip the guest instructions
-            if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+            if "A_GUEST" in hex_common.attribdict[tag]:
                 continue
             ## Skip instructions that saturate in a ternary expression
-            if ( tag in {'S2_asr_r_r_sat', 'S2_asl_r_r_sat'} ) :
+            if tag in {"S2_asr_r_r_sat", "S2_asl_r_r_sat"}:
                 continue
             ## Skip instructions using switch
-            if ( tag in {'S4_vrcrotate_acc', 'S4_vrcrotate'} ) :
+            if tag in {"S4_vrcrotate_acc", "S4_vrcrotate"}:
                 continue
             ## Skip trap instructions
-            if ( tag in {'J2_trap0', 'J2_trap1'} ) :
+            if tag in {"J2_trap0", "J2_trap1"}:
                 continue
             ## Skip 128-bit instructions
-            if ( tag in {'A7_croundd_ri', 'A7_croundd_rr'} ) :
+            if tag in {"A7_croundd_ri", "A7_croundd_rr"}:
                 continue
-            if ( tag in {'M7_wcmpyrw', 'M7_wcmpyrwc',
-                         'M7_wcmpyiw', 'M7_wcmpyiwc',
-                         'M7_wcmpyrw_rnd', 'M7_wcmpyrwc_rnd',
-                         'M7_wcmpyiw_rnd', 'M7_wcmpyiwc_rnd'} ) :
+            if tag in {
+                "M7_wcmpyrw",
+                "M7_wcmpyrwc",
+                "M7_wcmpyiw",
+                "M7_wcmpyiwc",
+                "M7_wcmpyrw_rnd",
+                "M7_wcmpyrwc_rnd",
+                "M7_wcmpyiw_rnd",
+                "M7_wcmpyiwc_rnd",
+            }:
                 continue
             ## Skip interleave/deinterleave instructions
-            if ( tag in {'S2_interleave', 'S2_deinterleave'} ) :
+            if tag in {"S2_interleave", "S2_deinterleave"}:
                 continue
             ## Skip instructions using bit reverse
-            if ( tag in {'S2_brev', 'S2_brevp', 'S2_ct0', 'S2_ct1',
-                         'S2_ct0p', 'S2_ct1p', 'A4_tlbmatch'} ) :
+            if tag in {
+                "S2_brev",
+                "S2_brevp",
+                "S2_ct0",
+                "S2_ct1",
+                "S2_ct0p",
+                "S2_ct1p",
+                "A4_tlbmatch",
+            }:
                 continue
             ## Skip other unsupported instructions
-            if ( tag == 'S2_cabacdecbin' or tag == 'A5_ACS' ) :
+            if tag == "S2_cabacdecbin" or tag == "A5_ACS":
                 continue
-            if ( tag.startswith('Y') ) :
+            if tag.startswith("Y"):
                 continue
-            if ( tag.startswith('V6_') ) :
+            if tag.startswith("V6_"):
                 continue
-            if ( tag.startswith('F') ) :
+            if tag.startswith("F"):
                 continue
-            if ( tag.endswith('_locked') ) :
+            if tag.endswith("_locked"):
                 continue
-            if ( "A_COF" in hex_common.attribdict[tag] ) :
+            if "A_COF" in hex_common.attribdict[tag]:
                 continue
 
             regs = tagregs[tag]
             imms = tagimms[tag]
 
             arguments = []
-            for regtype,regid,toss,numregs in regs:
+            for regtype, regid, toss, numregs in regs:
                 prefix = "in " if hex_common.is_read(regid) else ""
 
                 is_pair = hex_common.is_pair(regid)
-                is_single_old = (hex_common.is_single(regid)
-                                 and hex_common.is_old_val(regtype, regid, tag))
-                is_single_new = (hex_common.is_single(regid)
-                                 and hex_common.is_new_val(regtype, regid, tag))
+                is_single_old = hex_common.is_single(regid) and hex_common.is_old_val(
+                    regtype, regid, tag
+                )
+                is_single_new = hex_common.is_single(regid) and hex_common.is_new_val(
+                    regtype, regid, tag
+                )
 
                 if is_pair or is_single_old:
-                    arguments.append("%s%s%sV" % (prefix, regtype, regid))
+                    arguments.append(f"{prefix}{regtype}{regid}V")
                 elif is_single_new:
-                    arguments.append("%s%s%sN" % (prefix, regtype, regid))
+                    arguments.append(f"{prefix}{regtype}{regid}N")
                 else:
-                    print("Bad register parse: ",regtype,regid,toss,numregs)
+                    print("Bad register parse: ", regtype, regid, toss, numregs)
 
-            for immlett,bits,immshift in imms:
+            for immlett, bits, immshift in imms:
                 arguments.append(hex_common.imm_name(immlett))
 
-            f.write("%s(%s) {\n" % (tag, ", ".join(arguments)))
-            f.write("    ");
+            f.write(f"{tag}({', '.join(arguments)}) {{\n")
+            f.write("    ")
             if hex_common.need_ea(tag):
-                f.write("size4u_t EA; ");
-            f.write("%s\n" % hex_common.semdict[tag])
+                f.write("size4u_t EA; ")
+            f.write(f"{hex_common.semdict[tag]}\n")
             f.write("}\n\n")
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_op_attribs.py b/target/hexagon/gen_op_attribs.py
index 6a1a1ca..41074b8 100755
--- a/target/hexagon/gen_op_attribs.py
+++ b/target/hexagon/gen_op_attribs.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@ import re
 import string
 import hex_common
 
+
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
@@ -30,10 +31,13 @@ def main():
     ##
     ##     Generate all the attributes associated with each instruction
     ##
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         for tag in hex_common.tags:
-            f.write('OP_ATTRIB(%s,ATTRIBS(%s))\n' % \
-                (tag, ','.join(sorted(hex_common.attribdict[tag]))))
+            f.write(
+                f"OP_ATTRIB({tag},ATTRIBS("
+                f'{",".join(sorted(hex_common.attribdict[tag]))}))\n'
+            )
+
 
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py
index e8137d4..42972c7 100755
--- a/target/hexagon/gen_op_regs.py
+++ b/target/hexagon/gen_op_regs.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -22,21 +22,25 @@ import re
 import string
 import hex_common
 
+
 ##
 ##     Generate the register and immediate operands for each instruction
 ##
 def calculate_regid_reg(tag):
-    def letter_inc(x): return chr(ord(x)+1)
-    ordered_implregs = [ 'SP','FP','LR' ]
-    srcdst_lett = 'X'
-    src_lett = 'S'
-    dst_lett = 'D'
+    def letter_inc(x):
+        return chr(ord(x) + 1)
+
+    ordered_implregs = ["SP", "FP", "LR"]
+    srcdst_lett = "X"
+    src_lett = "S"
+    dst_lett = "D"
     retstr = ""
     mapdict = {}
     for reg in ordered_implregs:
         reg_rd = 0
         reg_wr = 0
-        if ('A_IMPLICIT_WRITES_'+reg) in hex_common.attribdict[tag]: reg_wr = 1
+        if ("A_IMPLICIT_WRITES_" + reg) in hex_common.attribdict[tag]:
+            reg_wr = 1
         if reg_rd and reg_wr:
             retstr += srcdst_lett
             mapdict[srcdst_lett] = reg
@@ -49,16 +53,19 @@ def calculate_regid_reg(tag):
             retstr += dst_lett
             mapdict[dst_lett] = reg
             dst_lett = letter_inc(dst_lett)
-    return retstr,mapdict
+    return retstr, mapdict
+
 
 def calculate_regid_letters(tag):
-    retstr,mapdict = calculate_regid_reg(tag)
+    retstr, mapdict = calculate_regid_reg(tag)
     return retstr
 
+
 def strip_reg_prefix(x):
-    y=x.replace('UREG.','')
-    y=y.replace('MREG.','')
-    return y.replace('GREG.','')
+    y = x.replace("UREG.", "")
+    y = y.replace("MREG.", "")
+    return y.replace("GREG.", "")
+
 
 def main():
     hex_common.read_semantics_file(sys.argv[1])
@@ -66,45 +73,51 @@ def main():
     tagregs = hex_common.get_tagregs()
     tagimms = hex_common.get_tagimms()
 
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         for tag in hex_common.tags:
             regs = tagregs[tag]
             rregs = []
             wregs = []
             regids = ""
-            for regtype,regid,toss,numregs in regs:
+            for regtype, regid, toss, numregs in regs:
                 if hex_common.is_read(regid):
-                    if regid[0] not in regids: regids += regid[0]
-                    rregs.append(regtype+regid+numregs)
+                    if regid[0] not in regids:
+                        regids += regid[0]
+                    rregs.append(regtype + regid + numregs)
                 if hex_common.is_written(regid):
-                    wregs.append(regtype+regid+numregs)
-                    if regid[0] not in regids: regids += regid[0]
+                    wregs.append(regtype + regid + numregs)
+                    if regid[0] not in regids:
+                        regids += regid[0]
             for attrib in hex_common.attribdict[tag]:
-                if hex_common.attribinfo[attrib]['rreg']:
-                    rregs.append(strip_reg_prefix(attribinfo[attrib]['rreg']))
-                if hex_common.attribinfo[attrib]['wreg']:
-                    wregs.append(strip_reg_prefix(attribinfo[attrib]['wreg']))
+                if hex_common.attribinfo[attrib]["rreg"]:
+                    rregs.append(strip_reg_prefix(attribinfo[attrib]["rreg"]))
+                if hex_common.attribinfo[attrib]["wreg"]:
+                    wregs.append(strip_reg_prefix(attribinfo[attrib]["wreg"]))
             regids += calculate_regid_letters(tag)
-            f.write('REGINFO(%s,"%s",\t/*RD:*/\t"%s",\t/*WR:*/\t"%s")\n' % \
-                (tag,regids,",".join(rregs),",".join(wregs)))
+            f.write(
+                f'REGINFO({tag},"{regids}",\t/*RD:*/\t"{",".join(rregs)}",'
+                f'\t/*WR:*/\t"{",".join(wregs)}")\n'
+            )
 
         for tag in hex_common.tags:
             imms = tagimms[tag]
-            f.write( 'IMMINFO(%s' % tag)
+            f.write(f"IMMINFO({tag}")
             if not imms:
-                f.write(''','u',0,0,'U',0,0''')
-            for sign,size,shamt in imms:
-                if sign == 'r': sign = 's'
+                f.write(""",'u',0,0,'U',0,0""")
+            for sign, size, shamt in imms:
+                if sign == "r":
+                    sign = "s"
                 if not shamt:
                     shamt = "0"
-                f.write(''','%s',%s,%s''' % (sign,size,shamt))
+                f.write(f""",'{sign}',{size},{shamt}""")
             if len(imms) == 1:
                 if sign.isupper():
-                    myu = 'u'
+                    myu = "u"
                 else:
-                    myu = 'U'
-                f.write(''','%s',0,0''' % myu)
-            f.write(')\n')
+                    myu = "U"
+                f.write(f""",'{myu}',0,0""")
+            f.write(")\n")
+
 
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_opcodes_def.py b/target/hexagon/gen_opcodes_def.py
index fa604a8..cddd868 100755
--- a/target/hexagon/gen_opcodes_def.py
+++ b/target/hexagon/gen_opcodes_def.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -22,15 +22,17 @@ import re
 import string
 import hex_common
 
+
 def main():
     hex_common.read_semantics_file(sys.argv[1])
 
     ##
     ##     Generate a list of all the opcodes
     ##
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         for tag in hex_common.tags:
-            f.write ( "OPCODE(%s),\n" % (tag) )
+            f.write(f"OPCODE({tag}),\n")
+
 
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_printinsn.py b/target/hexagon/gen_printinsn.py
index 12737bf..e570bd7 100755
--- a/target/hexagon/gen_printinsn.py
+++ b/target/hexagon/gen_printinsn.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -22,24 +22,26 @@ import re
 import string
 import hex_common
 
+
 ##
 ##     Generate data for printing each instruction (format string + operands)
 ##
 def regprinter(m):
     str = m.group(1)
-    str += ":".join(["%d"]*len(m.group(2)))
+    str += ":".join(["%d"] * len(m.group(2)))
     str += m.group(3)
-    if ('S' in m.group(1)) and (len(m.group(2)) == 1):
+    if ("S" in m.group(1)) and (len(m.group(2)) == 1):
         str += "/%s"
-    elif ('C' in m.group(1)) and (len(m.group(2)) == 1):
+    elif ("C" in m.group(1)) and (len(m.group(2)) == 1):
         str += "/%s"
     return str
 
+
 def spacify(s):
     # Regular expression that matches any operator that contains '=' character:
-    opswithequal_re = '[-+^&|!<>=]?='
+    opswithequal_re = "[-+^&|!<>=]?="
     # Regular expression that matches any assignment operator.
-    assignment_re = '[-+^&|]?='
+    assignment_re = "[-+^&|]?="
 
     # Out of the operators that contain the = sign, if the operator is also an
     # assignment, spaces will be added around it, unless it's enclosed within
@@ -54,9 +56,9 @@ def spacify(s):
     pc = 0
     while i < slen:
         c = s[i]
-        if c == '(':
+        if c == "(":
             pc += 1
-        elif c == ')':
+        elif c == ")":
             pc -= 1
         paren_count[i] = pc
         i += 1
@@ -76,31 +78,33 @@ def spacify(s):
         if paren_count[ms] == 0:
             # Check if the entire string t is an assignment.
             am = assign.match(t)
-            if am and len(am.group(0)) == me-ms:
+            if am and len(am.group(0)) == me - ms:
                 # Don't add spaces if they are already there.
-                if ms > 0 and s[ms-1] != ' ':
-                    out.append(' ')
+                if ms > 0 and s[ms - 1] != " ":
+                    out.append(" ")
                 out += t
-                if me < slen and s[me] != ' ':
-                    out.append(' ')
+                if me < slen and s[me] != " ":
+                    out.append(" ")
                 continue
         # If this is not an assignment, just append it to the output
         # string.
         out += t
 
     # Append the remaining part of the string.
-    out += s[pos:len(s)]
-    return ''.join(out)
+    out += s[pos : len(s)]
+    return "".join(out)
+
 
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
 
-    immext_casere = re.compile(r'IMMEXT\(([A-Za-z])')
+    immext_casere = re.compile(r"IMMEXT\(([A-Za-z])")
 
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         for tag in hex_common.tags:
-            if not hex_common.behdict[tag]: continue
+            if not hex_common.behdict[tag]:
+                continue
             extendable_upper_imm = False
             extendable_lower_imm = False
             m = immext_casere.search(hex_common.semdict[tag])
@@ -110,46 +114,45 @@ def main():
                 else:
                     extendable_lower_imm = True
             beh = hex_common.behdict[tag]
-            beh = hex_common.regre.sub(regprinter,beh)
-            beh = hex_common.absimmre.sub(r"#%s0x%x",beh)
-            beh = hex_common.relimmre.sub(r"PC+%s%d",beh)
+            beh = hex_common.regre.sub(regprinter, beh)
+            beh = hex_common.absimmre.sub(r"#%s0x%x", beh)
+            beh = hex_common.relimmre.sub(r"PC+%s%d", beh)
             beh = spacify(beh)
             # Print out a literal "%s" at the end, used to match empty string
             # so C won't complain at us
-            if ("A_VECX" in hex_common.attribdict[tag]):
+            if "A_VECX" in hex_common.attribdict[tag]:
                 macname = "DEF_VECX_PRINTINFO"
-            else: macname = "DEF_PRINTINFO"
-            f.write('%s(%s,"%s%%s"' % (macname,tag,beh))
-            regs_or_imms = \
-                hex_common.reg_or_immre.findall(hex_common.behdict[tag])
+            else:
+                macname = "DEF_PRINTINFO"
+            f.write(f'{macname}({tag},"{beh}%s"')
+            regs_or_imms = hex_common.reg_or_immre.findall(hex_common.behdict[tag])
             ri = 0
             seenregs = {}
-            for allregs,a,b,c,d,allimm,immlett,bits,immshift in regs_or_imms:
+            for allregs, a, b, c, d, allimm, immlett, bits, immshift in regs_or_imms:
                 if a:
-                    #register
+                    # register
                     if b in seenregs:
                         regno = seenregs[b]
                     else:
                         regno = ri
                     if len(b) == 1:
-                        f.write(', insn->regno[%d]' % regno)
-                        if 'S' in a:
-                            f.write(', sreg2str(insn->regno[%d])' % regno)
-                        elif 'C' in a:
-                            f.write(', creg2str(insn->regno[%d])' % regno)
+                        f.write(f", insn->regno[{regno}]")
+                        if "S" in a:
+                            f.write(f", sreg2str(insn->regno[{regno}])")
+                        elif "C" in a:
+                            f.write(f", creg2str(insn->regno[{regno}])")
                     elif len(b) == 2:
-                        f.write(', insn->regno[%d] + 1, insn->regno[%d]' % \
-                            (regno,regno))
+                        f.write(f", insn->regno[{regno}] + 1" f", insn->regno[{regno}]")
                     else:
                         print("Put some stuff to handle quads here")
                     if b not in seenregs:
                         seenregs[b] = ri
                         ri += 1
                 else:
-                    #immediate
-                    if (immlett.isupper()):
+                    # immediate
+                    if immlett.isupper():
                         if extendable_upper_imm:
-                            if immlett in 'rR':
+                            if immlett in "rR":
                                 f.write(',insn->extension_valid?"##":""')
                             else:
                                 f.write(',insn->extension_valid?"#":""')
@@ -158,16 +161,17 @@ def main():
                         ii = 1
                     else:
                         if extendable_lower_imm:
-                            if immlett in 'rR':
+                            if immlett in "rR":
                                 f.write(',insn->extension_valid?"##":""')
                             else:
                                 f.write(',insn->extension_valid?"#":""')
                         else:
                             f.write(',""')
                         ii = 0
-                    f.write(', insn->immed[%d]' % ii)
+                    f.write(f", insn->immed[{ii}]")
             # append empty string so there is at least one more arg
             f.write(',"")\n')
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_shortcode.py b/target/hexagon/gen_shortcode.py
index 9b589d0..deb9444 100755
--- a/target/hexagon/gen_shortcode.py
+++ b/target/hexagon/gen_shortcode.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -22,8 +22,10 @@ import re
 import string
 import hex_common
 
+
 def gen_shortcode(f, tag):
-    f.write('DEF_SHORTCODE(%s, %s)\n' % (tag, hex_common.semdict[tag]))
+    f.write(f"DEF_SHORTCODE({tag}, {hex_common.semdict[tag]})\n")
+
 
 def main():
     hex_common.read_semantics_file(sys.argv[1])
@@ -32,29 +34,30 @@ def main():
     tagregs = hex_common.get_tagregs()
     tagimms = hex_common.get_tagimms()
 
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         f.write("#ifndef DEF_SHORTCODE\n")
         f.write("#define DEF_SHORTCODE(TAG,SHORTCODE)    /* Nothing */\n")
         f.write("#endif\n")
 
         for tag in hex_common.tags:
             ## Skip the priv instructions
-            if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+            if "A_PRIV" in hex_common.attribdict[tag]:
                 continue
             ## Skip the guest instructions
-            if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+            if "A_GUEST" in hex_common.attribdict[tag]:
                 continue
             ## Skip the diag instructions
-            if ( tag == "Y6_diag" ) :
+            if tag == "Y6_diag":
                 continue
-            if ( tag == "Y6_diag0" ) :
+            if tag == "Y6_diag0":
                 continue
-            if ( tag == "Y6_diag1" ) :
+            if tag == "Y6_diag1":
                 continue
 
             gen_shortcode(f, tag)
 
         f.write("#undef DEF_SHORTCODE\n")
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index bcf0cf4..329e7a1 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -487,6 +487,19 @@
 #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
     fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
 
+/* dczeroa clears the 32 byte cache line at the address given */
+#define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE
+
+/* In linux-user mode, these are not modelled, suppress compiler warning */
+#define fGEN_TCG_Y2_dcinva(SHORTCODE) \
+    do { RsV = RsV; } while (0)
+#define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \
+    do { RsV = RsV; } while (0)
+#define fGEN_TCG_Y2_dccleana(SHORTCODE) \
+    do { RsV = RsV; } while (0)
+#define fGEN_TCG_Y2_icinva(SHORTCODE) \
+    do { RsV = RsV; } while (0)
+
 /*
  * dealloc_return
  * Assembler mapped to
@@ -1039,11 +1052,11 @@
 
 /* r0 = asr(r1, r2):sat */
 #define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
-    gen_asr_r_r_sat(RdV, RsV, RtV)
+    gen_asr_r_r_sat(ctx, RdV, RsV, RtV)
 
 /* r0 = asl(r1, r2):sat */
 #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
-    gen_asl_r_r_sat(RdV, RsV, RtV)
+    gen_asl_r_r_sat(ctx, RdV, RsV, RtV)
 
 #define fGEN_TCG_SL2_jumpr31(SHORTCODE) \
     gen_jumpr(ctx, hex_gpr[HEX_REG_LR])
@@ -1058,6 +1071,30 @@
 #define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \
     gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0])
 
+/* Count trailing zeros/ones */
+#define fGEN_TCG_S2_ct0(SHORTCODE) \
+    do { \
+        tcg_gen_ctzi_tl(RdV, RsV, 32); \
+    } while (0)
+#define fGEN_TCG_S2_ct1(SHORTCODE) \
+    do { \
+        tcg_gen_not_tl(RdV, RsV); \
+        tcg_gen_ctzi_tl(RdV, RdV, 32); \
+    } while (0)
+#define fGEN_TCG_S2_ct0p(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_ctzi_i64(tmp, RssV, 64); \
+        tcg_gen_extrl_i64_i32(RdV, tmp); \
+    } while (0)
+#define fGEN_TCG_S2_ct1p(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_not_i64(tmp, RssV); \
+        tcg_gen_ctzi_i64(tmp, tmp, 64); \
+        tcg_gen_extrl_i64_i32(RdV, tmp); \
+    } while (0)
+
 /* Floating point */
 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
     gen_helper_conv_sf2df(RddV, cpu_env, RsV)
@@ -1187,6 +1224,17 @@
     do { \
         RsV = RsV; \
     } while (0)
+#define fGEN_TCG_Y2_isync(SHORTCODE) \
+    do { } while (0)
+#define fGEN_TCG_Y2_barrier(SHORTCODE) \
+    do { } while (0)
+#define fGEN_TCG_Y2_syncht(SHORTCODE) \
+    do { } while (0)
+#define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
+    do { \
+        RsV = RsV; \
+        uiV = uiV; \
+    } while (0)
 
 #define fGEN_TCG_J2_trap0(SHORTCODE) \
     do { \
diff --git a/target/hexagon/gen_tcg_func_table.py b/target/hexagon/gen_tcg_func_table.py
index 4809d32..f998ef0 100755
--- a/target/hexagon/gen_tcg_func_table.py
+++ b/target/hexagon/gen_tcg_func_table.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ##
-##  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+##  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
 ##
 ##  This program is free software; you can redistribute it and/or modify
 ##  it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@ import re
 import string
 import hex_common
 
+
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
@@ -29,30 +30,31 @@ def main():
     tagregs = hex_common.get_tagregs()
     tagimms = hex_common.get_tagimms()
 
-    with open(sys.argv[3], 'w') as f:
+    with open(sys.argv[3], "w") as f:
         f.write("#ifndef HEXAGON_FUNC_TABLE_H\n")
         f.write("#define HEXAGON_FUNC_TABLE_H\n\n")
 
         f.write("const SemanticInsn opcode_genptr[XX_LAST_OPCODE] = {\n")
         for tag in hex_common.tags:
             ## Skip the priv instructions
-            if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+            if "A_PRIV" in hex_common.attribdict[tag]:
                 continue
             ## Skip the guest instructions
-            if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+            if "A_GUEST" in hex_common.attribdict[tag]:
                 continue
             ## Skip the diag instructions
-            if ( tag == "Y6_diag" ) :
+            if tag == "Y6_diag":
                 continue
-            if ( tag == "Y6_diag0" ) :
+            if tag == "Y6_diag0":
                 continue
-            if ( tag == "Y6_diag1" ) :
+            if tag == "Y6_diag1":
                 continue
 
-            f.write("    [%s] = generate_%s,\n" % (tag, tag))
+            f.write(f"    [{tag}] = generate_{tag},\n")
         f.write("};\n\n")
 
         f.write("#endif    /* HEXAGON_FUNC_TABLE_H */\n")
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index fa93e18..fcb3384 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -22,426 +22,452 @@ import re
 import string
 import hex_common
 
+
 ##
 ## Helpers for gen_tcg_func
 ##
 def gen_decl_ea_tcg(f, tag):
     f.write("    TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")
 
+
 def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
-    regN="%s%sN" % (regtype,regid)
-    if (regtype == "R"):
-        f.write("    const int %s = insn->regno[%d];\n" % (regN, regno))
-    elif (regtype == "C"):
-        f.write("    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-            (regN, regno))
+    regN = f"{regtype}{regid}N"
+    if regtype == "R":
+        f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+    elif regtype == "C":
+        f.write(f"    const int {regN} = insn->regno[{regno}] + HEX_REG_SA0;\n")
     else:
         print("Bad register parse: ", regtype, regid)
-    f.write("    TCGv_i64 %s%sV = get_result_gpr_pair(ctx, %s);\n" % \
-        (regtype, regid, regN))
+    f.write(f"    TCGv_i64 {regtype}{regid}V = " f"get_result_gpr_pair(ctx, {regN});\n")
+
 
 def genptr_decl_writable(f, tag, regtype, regid, regno):
-    regN="%s%sN" % (regtype,regid)
-    if (regtype == "R"):
-        f.write("    const int %s = insn->regno[%d];\n" % (regN, regno))
-        f.write("    TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \
-            (regtype, regid, regN))
-    elif (regtype == "C"):
-        f.write("    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-            (regN, regno))
-        f.write("    TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \
-            (regtype, regid, regN))
-    elif (regtype == "P"):
-        f.write("    const int %s = insn->regno[%d];\n" % (regN, regno))
-        f.write("    TCGv %s%sV = tcg_temp_new();\n" % \
-            (regtype, regid))
+    regN = f"{regtype}{regid}N"
+    if regtype == "R":
+        f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+        f.write(f"    TCGv {regtype}{regid}V = get_result_gpr(ctx, {regN});\n")
+    elif regtype == "C":
+        f.write(f"    const int {regN} = insn->regno[{regno}] + HEX_REG_SA0;\n")
+        f.write(f"    TCGv {regtype}{regid}V = get_result_gpr(ctx, {regN});\n")
+    elif regtype == "P":
+        f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+        f.write(f"    TCGv {regtype}{regid}V = tcg_temp_new();\n")
     else:
         print("Bad register parse: ", regtype, regid)
 
+
 def genptr_decl(f, tag, regtype, regid, regno):
-    regN="%s%sN" % (regtype,regid)
-    if (regtype == "R"):
-        if (regid in {"ss", "tt"}):
-            f.write("    TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
-                (regtype, regid))
-            f.write("    const int %s = insn->regno[%d];\n" % \
-                (regN, regno))
-        elif (regid in {"dd", "ee", "xx", "yy"}):
+    regN = f"{regtype}{regid}N"
+    if regtype == "R":
+        if regid in {"ss", "tt"}:
+            f.write(f"    TCGv_i64 {regtype}{regid}V = tcg_temp_new_i64();\n")
+            f.write(f"    const int {regN} = insn->regno[{regno}];\n")
+        elif regid in {"dd", "ee", "xx", "yy"}:
             genptr_decl_pair_writable(f, tag, regtype, regid, regno)
-        elif (regid in {"s", "t", "u", "v"}):
-            f.write("    TCGv %s%sV = hex_gpr[insn->regno[%d]];\n" % \
-                (regtype, regid, regno))
-        elif (regid in {"d", "e", "x", "y"}):
+        elif regid in {"s", "t", "u", "v"}:
+            f.write(
+                f"    TCGv {regtype}{regid}V = " f"hex_gpr[insn->regno[{regno}]];\n"
+            )
+        elif regid in {"d", "e", "x", "y"}:
             genptr_decl_writable(f, tag, regtype, regid, regno)
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid in {"s", "t", "u", "v"}):
-            f.write("    TCGv %s%sV = hex_pred[insn->regno[%d]];\n" % \
-                (regtype, regid, regno))
-        elif (regid in {"d", "e", "x"}):
+    elif regtype == "P":
+        if regid in {"s", "t", "u", "v"}:
+            f.write(
+                f"    TCGv {regtype}{regid}V = " f"hex_pred[insn->regno[{regno}]];\n"
+            )
+        elif regid in {"d", "e", "x"}:
             genptr_decl_writable(f, tag, regtype, regid, regno)
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "C"):
-        if (regid == "ss"):
-            f.write("    TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
-                (regtype, regid))
-            f.write("    const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
-                (regN, regno))
-        elif (regid == "dd"):
+    elif regtype == "C":
+        if regid == "ss":
+            f.write(f"    TCGv_i64 {regtype}{regid}V = " f"tcg_temp_new_i64();\n")
+            f.write(f"    const int {regN} = insn->regno[{regno}] + " "HEX_REG_SA0;\n")
+        elif regid == "dd":
             genptr_decl_pair_writable(f, tag, regtype, regid, regno)
-        elif (regid == "s"):
-            f.write("    TCGv %s%sV = tcg_temp_new();\n" % \
-                (regtype, regid))
-            f.write("    const int %s%sN = insn->regno[%d] + HEX_REG_SA0;\n" % \
-                (regtype, regid, regno))
-        elif (regid == "d"):
+        elif regid == "s":
+            f.write(f"    TCGv {regtype}{regid}V = tcg_temp_new();\n")
+            f.write(
+                f"    const int {regtype}{regid}N = insn->regno[{regno}] + "
+                "HEX_REG_SA0;\n"
+            )
+        elif regid == "d":
             genptr_decl_writable(f, tag, regtype, regid, regno)
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "M"):
-        if (regid == "u"):
-            f.write("    const int %s%sN = insn->regno[%d];\n"% \
-                (regtype, regid, regno))
-            f.write("    TCGv %s%sV = hex_gpr[%s%sN + HEX_REG_M0];\n" % \
-                (regtype, regid, regtype, regid))
+    elif regtype == "M":
+        if regid == "u":
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(
+                f"    TCGv {regtype}{regid}V = hex_gpr[{regtype}{regid}N + "
+                "HEX_REG_M0];\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "V"):
-        if (regid in {"dd"}):
-            f.write("    const int %s%sN = insn->regno[%d];\n" %\
-                (regtype, regid, regno))
-            f.write("    const intptr_t %s%sV_off =\n" %\
-                 (regtype, regid))
-            if (hex_common.is_tmp_result(tag)):
-                f.write("        ctx_tmp_vreg_off(ctx, %s%sN, 2, true);\n" % \
-                     (regtype, regid))
+    elif regtype == "V":
+        if regid in {"dd"}:
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(f"    const intptr_t {regtype}{regid}V_off =\n")
+            if hex_common.is_tmp_result(tag):
+                f.write(
+                    f"        ctx_tmp_vreg_off(ctx, {regtype}{regid}N, 2, " "true);\n"
+                )
             else:
-                f.write("        ctx_future_vreg_off(ctx, %s%sN," % \
-                     (regtype, regid))
+                f.write(f"        ctx_future_vreg_off(ctx, {regtype}{regid}N,")
                 f.write(" 2, true);\n")
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
-                    (regtype, regid))
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                    (regtype, regid, regtype, regid))
-        elif (regid in {"uu", "vv", "xx"}):
-            f.write("    const int %s%sN = insn->regno[%d];\n" % \
-                (regtype, regid, regno))
-            f.write("    const intptr_t %s%sV_off =\n" % \
-                 (regtype, regid))
-            f.write("        offsetof(CPUHexagonState, %s%sV);\n" % \
-                 (regtype, regid))
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
-                    (regtype, regid))
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                    (regtype, regid, regtype, regid))
-        elif (regid in {"s", "u", "v", "w"}):
-            f.write("    const int %s%sN = insn->regno[%d];\n" % \
-                (regtype, regid, regno))
-            f.write("    const intptr_t %s%sV_off =\n" % \
-                              (regtype, regid))
-            f.write("        vreg_src_off(ctx, %s%sN);\n" % \
-                              (regtype, regid))
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
-                    (regtype, regid))
-        elif (regid in {"d", "x", "y"}):
-            f.write("    const int %s%sN = insn->regno[%d];\n" % \
-                (regtype, regid, regno))
-            f.write("    const intptr_t %s%sV_off =\n" % \
-                (regtype, regid))
-            if (regid == "y"):
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(f"    TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
+                f.write(
+                    f"    tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+                    f"{regtype}{regid}V_off);\n"
+                )
+        elif regid in {"uu", "vv", "xx"}:
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(f"    const intptr_t {regtype}{regid}V_off =\n")
+            f.write(f"        offsetof(CPUHexagonState, {regtype}{regid}V);\n")
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(f"    TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
+                f.write(
+                    f"    tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+                    f"{regtype}{regid}V_off);\n"
+                )
+        elif regid in {"s", "u", "v", "w"}:
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(f"    const intptr_t {regtype}{regid}V_off =\n")
+            f.write(f"        vreg_src_off(ctx, {regtype}{regid}N);\n")
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(f"    TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
+        elif regid in {"d", "x", "y"}:
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(f"    const intptr_t {regtype}{regid}V_off =\n")
+            if regid == "y":
                 f.write("        offsetof(CPUHexagonState, vtmp);\n")
-            elif (hex_common.is_tmp_result(tag)):
-                f.write("        ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n" % \
-                    (regtype, regid))
+            elif hex_common.is_tmp_result(tag):
+                f.write(
+                    f"        ctx_tmp_vreg_off(ctx, {regtype}{regid}N, 1, " "true);\n"
+                )
             else:
-                f.write("        ctx_future_vreg_off(ctx, %s%sN," % \
-                    (regtype, regid))
-                f.write(" 1, true);\n");
-
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
-                    (regtype, regid))
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                    (regtype, regid, regtype, regid))
+                f.write(f"        ctx_future_vreg_off(ctx, {regtype}{regid}N,")
+                f.write(" 1, true);\n")
+
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(f"    TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
+                f.write(
+                    f"    tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+                    f"{regtype}{regid}V_off);\n"
+                )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "Q"):
-        if (regid in {"d", "e", "x"}):
-            f.write("    const int %s%sN = insn->regno[%d];\n" % \
-                (regtype, regid, regno))
-            f.write("    const intptr_t %s%sV_off =\n" % \
-                (regtype, regid))
-            f.write("        get_result_qreg(ctx, %s%sN);\n" % \
-                (regtype, regid))
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
-                    (regtype, regid))
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                    (regtype, regid, regtype, regid))
-        elif (regid in {"s", "t", "u", "v"}):
-            f.write("    const int %s%sN = insn->regno[%d];\n" % \
-                (regtype, regid, regno))
-            f.write("    const intptr_t %s%sV_off =\n" %\
-                (regtype, regid))
-            f.write("        offsetof(CPUHexagonState, QRegs[%s%sN]);\n" % \
-                (regtype, regid))
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \
-                    (regtype, regid))
+    elif regtype == "Q":
+        if regid in {"d", "e", "x"}:
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(f"    const intptr_t {regtype}{regid}V_off =\n")
+            f.write(f"        get_result_qreg(ctx, {regtype}{regid}N);\n")
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(f"    TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
+                f.write(
+                    f"    tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+                    f"{regtype}{regid}V_off);\n"
+                )
+        elif regid in {"s", "t", "u", "v"}:
+            f.write(f"    const int {regtype}{regid}N = " f"insn->regno[{regno}];\n")
+            f.write(f"    const intptr_t {regtype}{regid}V_off =\n")
+            f.write(
+                f"        offsetof(CPUHexagonState, " f"QRegs[{regtype}{regid}N]);\n"
+            )
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(f"    TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
         else:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
+
 def genptr_decl_new(f, tag, regtype, regid, regno):
-    if (regtype == "N"):
-        if (regid in {"s", "t"}):
-            f.write("    TCGv %s%sN = hex_new_value[insn->regno[%d]];\n" % \
-                (regtype, regid, regno))
+    if regtype == "N":
+        if regid in {"s", "t"}:
+            f.write(
+                f"    TCGv {regtype}{regid}N = "
+                f"hex_new_value[insn->regno[{regno}]];\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid in {"t", "u", "v"}):
-            f.write("    TCGv %s%sN = hex_new_pred_value[insn->regno[%d]];\n" % \
-                (regtype, regid, regno))
+    elif regtype == "P":
+        if regid in {"t", "u", "v"}:
+            f.write(
+                f"    TCGv {regtype}{regid}N = "
+                f"hex_new_pred_value[insn->regno[{regno}]];\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "O"):
-        if (regid == "s"):
-            f.write("    const intptr_t %s%sN_num = insn->regno[%d];\n" % \
-                (regtype, regid, regno))
-            if (hex_common.skip_qemu_helper(tag)):
-                f.write("    const intptr_t %s%sN_off =\n" % \
-                    (regtype, regid))
-                f.write("         ctx_future_vreg_off(ctx, %s%sN_num," % \
-                    (regtype, regid))
+    elif regtype == "O":
+        if regid == "s":
+            f.write(
+                f"    const intptr_t {regtype}{regid}N_num = "
+                f"insn->regno[{regno}];\n"
+            )
+            if hex_common.skip_qemu_helper(tag):
+                f.write(f"    const intptr_t {regtype}{regid}N_off =\n")
+                f.write("         ctx_future_vreg_off(ctx, " f"{regtype}{regid}N_num,")
                 f.write(" 1, true);\n")
             else:
-                f.write("    TCGv %s%sN = tcg_constant_tl(%s%sN_num);\n" % \
-                    (regtype, regid, regtype, regid))
+                f.write(
+                    f"    TCGv {regtype}{regid}N = "
+                    f"tcg_constant_tl({regtype}{regid}N_num);\n"
+                )
         else:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
+
 def genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i):
-    if (hex_common.is_pair(regid)):
+    if hex_common.is_pair(regid):
         genptr_decl(f, tag, regtype, regid, i)
-    elif (hex_common.is_single(regid)):
+    elif hex_common.is_single(regid):
         if hex_common.is_old_val(regtype, regid, tag):
-            genptr_decl(f,tag, regtype, regid, i)
+            genptr_decl(f, tag, regtype, regid, i)
         elif hex_common.is_new_val(regtype, regid, tag):
             genptr_decl_new(f, tag, regtype, regid, i)
         else:
-            print("Bad register parse: ",regtype,regid,toss,numregs)
+            print("Bad register parse: ", regtype, regid, toss, numregs)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
 
-def genptr_decl_imm(f,immlett):
-    if (immlett.isupper()):
+
+def genptr_decl_imm(f, immlett):
+    if immlett.isupper():
         i = 1
     else:
         i = 0
-    f.write("    int %s = insn->immed[%d];\n" % \
-        (hex_common.imm_name(immlett), i))
+    f.write(f"    int {hex_common.imm_name(immlett)} = insn->immed[{i}];\n")
+
 
 def genptr_src_read(f, tag, regtype, regid):
-    if (regtype == "R"):
-        if (regid in {"ss", "tt", "xx", "yy"}):
-            f.write("    tcg_gen_concat_i32_i64(%s%sV, hex_gpr[%s%sN],\n" % \
-                (regtype, regid, regtype, regid))
-            f.write("                                 hex_gpr[%s%sN + 1]);\n" % \
-                (regtype, regid))
-        elif (regid in {"x", "y"}):
+    if regtype == "R":
+        if regid in {"ss", "tt", "xx", "yy"}:
+            f.write(
+                f"    tcg_gen_concat_i32_i64({regtype}{regid}V, "
+                f"hex_gpr[{regtype}{regid}N],\n"
+            )
+            f.write(
+                f"                                 hex_gpr[{regtype}"
+                f"{regid}N + 1]);\n"
+            )
+        elif regid in {"x", "y"}:
             ## For read/write registers, we need to get the original value into
             ## the result TCGv.  For conditional instructions, this is done in
             ## gen_start_packet.  For unconditional instructions, we do it here.
-            if ('A_CONDEXEC' not in hex_common.attribdict[tag]):
-                f.write("    tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \
-                    (regtype, regid, regtype, regid))
-        elif (regid not in {"s", "t", "u", "v"}):
+            if "A_CONDEXEC" not in hex_common.attribdict[tag]:
+                f.write(
+                    f"    tcg_gen_mov_tl({regtype}{regid}V, "
+                    f"hex_gpr[{regtype}{regid}N]);\n"
+                )
+        elif regid not in {"s", "t", "u", "v"}:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid == "x"):
-            f.write("    tcg_gen_mov_tl(%s%sV, hex_pred[%s%sN]);\n" % \
-                (regtype, regid, regtype, regid))
-        elif (regid not in {"s", "t", "u", "v"}):
+    elif regtype == "P":
+        if regid == "x":
+            f.write(
+                f"    tcg_gen_mov_tl({regtype}{regid}V, "
+                f"hex_pred[{regtype}{regid}N]);\n"
+            )
+        elif regid not in {"s", "t", "u", "v"}:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "C"):
-        if (regid == "ss"):
-            f.write("    gen_read_ctrl_reg_pair(ctx, %s%sN, %s%sV);\n" % \
-                             (regtype, regid, regtype, regid))
-        elif (regid == "s"):
-            f.write("    gen_read_ctrl_reg(ctx, %s%sN, %s%sV);\n" % \
-                             (regtype, regid, regtype, regid))
+    elif regtype == "C":
+        if regid == "ss":
+            f.write(
+                f"    gen_read_ctrl_reg_pair(ctx, {regtype}{regid}N, "
+                f"{regtype}{regid}V);\n"
+            )
+        elif regid == "s":
+            f.write(
+                f"    gen_read_ctrl_reg(ctx, {regtype}{regid}N, "
+                f"{regtype}{regid}V);\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "M"):
-        if (regid != "u"):
+    elif regtype == "M":
+        if regid != "u":
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "V"):
-        if (regid in {"uu", "vv", "xx"}):
-            f.write("    tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
-                (regtype, regid))
-            f.write("        vreg_src_off(ctx, %s%sN),\n" % \
-                (regtype, regid))
+    elif regtype == "V":
+        if regid in {"uu", "vv", "xx"}:
+            f.write(f"    tcg_gen_gvec_mov(MO_64, {regtype}{regid}V_off,\n")
+            f.write(f"        vreg_src_off(ctx, {regtype}{regid}N),\n")
             f.write("        sizeof(MMVector), sizeof(MMVector));\n")
             f.write("    tcg_gen_gvec_mov(MO_64,\n")
-            f.write("        %s%sV_off + sizeof(MMVector),\n" % \
-                (regtype, regid))
-            f.write("        vreg_src_off(ctx, %s%sN ^ 1),\n" % \
-                (regtype, regid))
+            f.write(f"        {regtype}{regid}V_off + sizeof(MMVector),\n")
+            f.write(f"        vreg_src_off(ctx, {regtype}{regid}N ^ 1),\n")
             f.write("        sizeof(MMVector), sizeof(MMVector));\n")
-        elif (regid in {"s", "u", "v", "w"}):
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                                 (regtype, regid, regtype, regid))
-        elif (regid in {"x", "y"}):
-            f.write("    tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
-                             (regtype, regid))
-            f.write("        vreg_src_off(ctx, %s%sN),\n" % \
-                             (regtype, regid))
+        elif regid in {"s", "u", "v", "w"}:
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(
+                    f"    tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+                    f"{regtype}{regid}V_off);\n"
+                )
+        elif regid in {"x", "y"}:
+            f.write(f"    tcg_gen_gvec_mov(MO_64, {regtype}{regid}V_off,\n")
+            f.write(f"        vreg_src_off(ctx, {regtype}{regid}N),\n")
             f.write("        sizeof(MMVector), sizeof(MMVector));\n")
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "Q"):
-        if (regid in {"s", "t", "u", "v"}):
-            if (not hex_common.skip_qemu_helper(tag)):
-                f.write("    tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \
-                    (regtype, regid, regtype, regid))
-        elif (regid in {"x"}):
-            f.write("    tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \
-                (regtype, regid))
-            f.write("        offsetof(CPUHexagonState, QRegs[%s%sN]),\n" % \
-                (regtype, regid))
+    elif regtype == "Q":
+        if regid in {"s", "t", "u", "v"}:
+            if not hex_common.skip_qemu_helper(tag):
+                f.write(
+                    f"    tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+                    f"{regtype}{regid}V_off);\n"
+                )
+        elif regid in {"x"}:
+            f.write(f"    tcg_gen_gvec_mov(MO_64, {regtype}{regid}V_off,\n")
+            f.write(
+                f"        offsetof(CPUHexagonState, " f"QRegs[{regtype}{regid}N]),\n"
+            )
             f.write("        sizeof(MMQReg), sizeof(MMQReg));\n")
         else:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
-def genptr_src_read_new(f,regtype,regid):
-    if (regtype == "N"):
-        if (regid not in {"s", "t"}):
+
+def genptr_src_read_new(f, regtype, regid):
+    if regtype == "N":
+        if regid not in {"s", "t"}:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid not in {"t", "u", "v"}):
+    elif regtype == "P":
+        if regid not in {"t", "u", "v"}:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "O"):
-        if (regid != "s"):
+    elif regtype == "O":
+        if regid != "s":
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
-def genptr_src_read_opn(f,regtype,regid,tag):
-    if (hex_common.is_pair(regid)):
+
+def genptr_src_read_opn(f, regtype, regid, tag):
+    if hex_common.is_pair(regid):
         genptr_src_read(f, tag, regtype, regid)
-    elif (hex_common.is_single(regid)):
+    elif hex_common.is_single(regid):
         if hex_common.is_old_val(regtype, regid, tag):
             genptr_src_read(f, tag, regtype, regid)
         elif hex_common.is_new_val(regtype, regid, tag):
-            genptr_src_read_new(f,regtype,regid)
+            genptr_src_read_new(f, regtype, regid)
         else:
-            print("Bad register parse: ",regtype,regid,toss,numregs)
+            print("Bad register parse: ", regtype, regid, toss, numregs)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
 
 def gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i):
-    if (i > 0): f.write(", ")
-    if (hex_common.is_pair(regid)):
-        f.write("%s%sV" % (regtype,regid))
-    elif (hex_common.is_single(regid)):
+    if i > 0:
+        f.write(", ")
+    if hex_common.is_pair(regid):
+        f.write(f"{regtype}{regid}V")
+    elif hex_common.is_single(regid):
         if hex_common.is_old_val(regtype, regid, tag):
-            f.write("%s%sV" % (regtype,regid))
+            f.write(f"{regtype}{regid}V")
         elif hex_common.is_new_val(regtype, regid, tag):
-            f.write("%s%sN" % (regtype,regid))
+            f.write(f"{regtype}{regid}N")
         else:
-            print("Bad register parse: ",regtype,regid,toss,numregs)
+            print("Bad register parse: ", regtype, regid, toss, numregs)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
+
+def gen_helper_decl_imm(f, immlett):
+    f.write(
+        f"    TCGv tcgv_{hex_common.imm_name(immlett)} = "
+        f"tcg_constant_tl({hex_common.imm_name(immlett)});\n"
+    )
 
-def gen_helper_decl_imm(f,immlett):
-    f.write("    TCGv tcgv_%s = tcg_constant_tl(%s);\n" % \
-        (hex_common.imm_name(immlett), hex_common.imm_name(immlett)))
 
-def gen_helper_call_imm(f,immlett):
-    f.write(", tcgv_%s" % hex_common.imm_name(immlett))
+def gen_helper_call_imm(f, immlett):
+    f.write(f", tcgv_{hex_common.imm_name(immlett)}")
+
 
 def genptr_dst_write_pair(f, tag, regtype, regid):
-    f.write("    gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \
-        (regtype, regid, regtype, regid))
+    f.write(f"    gen_log_reg_write_pair({regtype}{regid}N, " f"{regtype}{regid}V);\n")
+
 
 def genptr_dst_write(f, tag, regtype, regid):
-    if (regtype == "R"):
-        if (regid in {"dd", "xx", "yy"}):
+    if regtype == "R":
+        if regid in {"dd", "xx", "yy"}:
             genptr_dst_write_pair(f, tag, regtype, regid)
-        elif (regid in {"d", "e", "x", "y"}):
-            f.write("    gen_log_reg_write(%s%sN, %s%sV);\n" % \
-                (regtype, regid, regtype, regid))
+        elif regid in {"d", "e", "x", "y"}:
+            f.write(
+                f"    gen_log_reg_write({regtype}{regid}N, " f"{regtype}{regid}V);\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "P"):
-        if (regid in {"d", "e", "x"}):
-            f.write("    gen_log_pred_write(ctx, %s%sN, %s%sV);\n" % \
-                (regtype, regid, regtype, regid))
+    elif regtype == "P":
+        if regid in {"d", "e", "x"}:
+            f.write(
+                f"    gen_log_pred_write(ctx, {regtype}{regid}N, "
+                f"{regtype}{regid}V);\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "C"):
-        if (regid == "dd"):
-            f.write("    gen_write_ctrl_reg_pair(ctx, %s%sN, %s%sV);\n" % \
-                             (regtype, regid, regtype, regid))
-        elif (regid == "d"):
-            f.write("    gen_write_ctrl_reg(ctx, %s%sN, %s%sV);\n" % \
-                             (regtype, regid, regtype, regid))
+    elif regtype == "C":
+        if regid == "dd":
+            f.write(
+                f"    gen_write_ctrl_reg_pair(ctx, {regtype}{regid}N, "
+                f"{regtype}{regid}V);\n"
+            )
+        elif regid == "d":
+            f.write(
+                f"    gen_write_ctrl_reg(ctx, {regtype}{regid}N, "
+                f"{regtype}{regid}V);\n"
+            )
         else:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
+
 def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"):
-    if (regtype == "V"):
-        if (regid in {"xx"}):
-            f.write("    gen_log_vreg_write_pair(ctx, %s%sV_off, %s%sN, " % \
-                (regtype, regid, regtype, regid))
-            f.write("%s);\n" % \
-                (newv))
-        elif (regid in {"y"}):
-            f.write("    gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s);\n" % \
-                (regtype, regid, regtype, regid, newv))
-        elif (regid not in {"dd", "d", "x"}):
+    if regtype == "V":
+        if regid in {"xx"}:
+            f.write(
+                f"    gen_log_vreg_write_pair(ctx, {regtype}{regid}V_off, "
+                f"{regtype}{regid}N, {newv});\n"
+            )
+        elif regid in {"y"}:
+            f.write(
+                f"    gen_log_vreg_write(ctx, {regtype}{regid}V_off, "
+                f"{regtype}{regid}N, {newv});\n"
+            )
+        elif regid not in {"dd", "d", "x"}:
             print("Bad register parse: ", regtype, regid)
-    elif (regtype == "Q"):
-        if (regid not in {"d", "e", "x"}):
+    elif regtype == "Q":
+        if regid not in {"d", "e", "x"}:
             print("Bad register parse: ", regtype, regid)
     else:
         print("Bad register parse: ", regtype, regid)
 
-def genptr_dst_write_opn(f,regtype, regid, tag):
-    if (hex_common.is_pair(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            if (hex_common.is_tmp_result(tag)):
+
+def genptr_dst_write_opn(f, regtype, regid, tag):
+    if hex_common.is_pair(regid):
+        if hex_common.is_hvx_reg(regtype):
+            if hex_common.is_tmp_result(tag):
                 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_TMP")
             else:
                 genptr_dst_write_ext(f, tag, regtype, regid)
         else:
             genptr_dst_write(f, tag, regtype, regid)
-    elif (hex_common.is_single(regid)):
-        if (hex_common.is_hvx_reg(regtype)):
-            if (hex_common.is_new_result(tag)):
+    elif hex_common.is_single(regid):
+        if hex_common.is_hvx_reg(regtype):
+            if hex_common.is_new_result(tag):
                 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_NEW")
-            elif (hex_common.is_tmp_result(tag)):
+            elif hex_common.is_tmp_result(tag):
                 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_TMP")
             else:
                 genptr_dst_write_ext(f, tag, regtype, regid, "EXT_DFL")
         else:
             genptr_dst_write(f, tag, regtype, regid)
     else:
-        print("Bad register parse: ",regtype,regid,toss,numregs)
+        print("Bad register parse: ", regtype, regid, toss, numregs)
+
 
 ##
 ## Generate the TCG code to call the helper
@@ -465,58 +491,60 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
 ##       <GEN>  is gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
 ##
 def gen_tcg_func(f, tag, regs, imms):
-    f.write("static void generate_%s(DisasContext *ctx)\n" %tag)
-    f.write('{\n')
+    f.write(f"static void generate_{tag}(DisasContext *ctx)\n")
+    f.write("{\n")
 
     f.write("    Insn *insn __attribute__((unused)) = ctx->insn;\n")
 
-    if hex_common.need_ea(tag): gen_decl_ea_tcg(f, tag)
-    i=0
+    if hex_common.need_ea(tag):
+        gen_decl_ea_tcg(f, tag)
+    i = 0
     ## Declare all the operands (regs and immediates)
-    for regtype,regid,toss,numregs in regs:
+    for regtype, regid, toss, numregs in regs:
         genptr_decl_opn(f, tag, regtype, regid, toss, numregs, i)
         i += 1
-    for immlett,bits,immshift in imms:
-        genptr_decl_imm(f,immlett)
+    for immlett, bits, immshift in imms:
+        genptr_decl_imm(f, immlett)
 
-    if 'A_PRIV' in hex_common.attribdict[tag]:
-        f.write('    fCHECKFORPRIV();\n')
-    if 'A_GUEST' in hex_common.attribdict[tag]:
-        f.write('    fCHECKFORGUEST();\n')
+    if "A_PRIV" in hex_common.attribdict[tag]:
+        f.write("    fCHECKFORPRIV();\n")
+    if "A_GUEST" in hex_common.attribdict[tag]:
+        f.write("    fCHECKFORGUEST();\n")
 
     ## Read all the inputs
-    for regtype,regid,toss,numregs in regs:
-        if (hex_common.is_read(regid)):
-            genptr_src_read_opn(f,regtype,regid,tag)
+    for regtype, regid, toss, numregs in regs:
+        if hex_common.is_read(regid):
+            genptr_src_read_opn(f, regtype, regid, tag)
 
     if hex_common.is_idef_parser_enabled(tag):
         declared = []
         ## Handle registers
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_pair(regid)
-                or (hex_common.is_single(regid)
-                    and hex_common.is_old_val(regtype, regid, tag))):
-                declared.append("%s%sV" % (regtype, regid))
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_pair(regid) or (
+                hex_common.is_single(regid)
+                and hex_common.is_old_val(regtype, regid, tag)
+            ):
+                declared.append(f"{regtype}{regid}V")
                 if regtype == "M":
-                    declared.append("%s%sN" % (regtype, regid))
+                    declared.append(f"{regtype}{regid}N")
             elif hex_common.is_new_val(regtype, regid, tag):
-                declared.append("%s%sN" % (regtype,regid))
+                declared.append(f"{regtype}{regid}N")
             else:
-                print("Bad register parse: ",regtype,regid,toss,numregs)
+                print("Bad register parse: ", regtype, regid, toss, numregs)
 
         ## Handle immediates
-        for immlett,bits,immshift in imms:
+        for immlett, bits, immshift in imms:
             declared.append(hex_common.imm_name(immlett))
 
         arguments = ", ".join(["ctx", "ctx->insn", "ctx->pkt"] + declared)
-        f.write("    emit_%s(%s);\n" % (tag, arguments))
+        f.write(f"    emit_{tag}({arguments});\n")
 
-    elif ( hex_common.skip_qemu_helper(tag) ):
-        f.write("    fGEN_TCG_%s(%s);\n" % (tag, hex_common.semdict[tag]))
+    elif hex_common.skip_qemu_helper(tag):
+        f.write(f"    fGEN_TCG_{tag}({hex_common.semdict[tag]});\n")
     else:
         ## Generate the call to the helper
-        for immlett,bits,immshift in imms:
-            gen_helper_decl_imm(f,immlett)
+        for immlett, bits, immshift in imms:
+            gen_helper_decl_imm(f, immlett)
         if hex_common.need_pkt_has_multi_cof(tag):
             f.write("    TCGv pkt_has_multi_cof = ")
             f.write("tcg_constant_tl(ctx->pkt->pkt_has_multi_cof);\n")
@@ -528,63 +556,69 @@ def gen_tcg_func(f, tag, regs, imms):
             f.write("    TCGv PC = tcg_constant_tl(ctx->pkt->pc);\n")
         if hex_common.helper_needs_next_PC(tag):
             f.write("    TCGv next_PC = tcg_constant_tl(ctx->next_PC);\n")
-        f.write("    gen_helper_%s(" % (tag))
-        i=0
+        f.write(f"    gen_helper_{tag}(")
+        i = 0
         ## If there is a scalar result, it is the return type
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
-                if (hex_common.is_hvx_reg(regtype)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
+                if hex_common.is_hvx_reg(regtype):
                     continue
                 gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
                 i += 1
-        if (i > 0): f.write(", ")
+        if i > 0:
+            f.write(", ")
         f.write("cpu_env")
-        i=1
+        i = 1
         ## For conditional instructions, we pass in the destination register
-        if 'A_CONDEXEC' in hex_common.attribdict[tag]:
+        if "A_CONDEXEC" in hex_common.attribdict[tag]:
             for regtype, regid, toss, numregs in regs:
-                if (hex_common.is_writeonly(regid) and
-                    not hex_common.is_hvx_reg(regtype)):
-                    gen_helper_call_opn(f, tag, regtype, regid, toss, \
-                                        numregs, i)
+                if hex_common.is_writeonly(regid) and not hex_common.is_hvx_reg(
+                    regtype
+                ):
+                    gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
                     i += 1
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_written(regid)):
-                if (not hex_common.is_hvx_reg(regtype)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_written(regid):
+                if not hex_common.is_hvx_reg(regtype):
                     continue
                 gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
                 i += 1
-        for regtype,regid,toss,numregs in regs:
-            if (hex_common.is_read(regid)):
-                if (hex_common.is_hvx_reg(regtype) and
-                    hex_common.is_readwrite(regid)):
+        for regtype, regid, toss, numregs in regs:
+            if hex_common.is_read(regid):
+                if hex_common.is_hvx_reg(regtype) and hex_common.is_readwrite(regid):
                     continue
                 gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i)
                 i += 1
-        for immlett,bits,immshift in imms:
-            gen_helper_call_imm(f,immlett)
+        for immlett, bits, immshift in imms:
+            gen_helper_call_imm(f, immlett)
 
         if hex_common.need_pkt_has_multi_cof(tag):
             f.write(", pkt_has_multi_cof")
-        if hex_common.need_PC(tag): f.write(", PC")
-        if hex_common.helper_needs_next_PC(tag): f.write(", next_PC")
-        if hex_common.need_slot(tag): f.write(", slot")
-        if hex_common.need_part1(tag): f.write(", part1" )
+        if hex_common.need_PC(tag):
+            f.write(", PC")
+        if hex_common.helper_needs_next_PC(tag):
+            f.write(", next_PC")
+        if hex_common.need_slot(tag):
+            f.write(", slot")
+        if hex_common.need_part1(tag):
+            f.write(", part1")
         f.write(");\n")
 
     ## Write all the outputs
-    for regtype,regid,toss,numregs in regs:
-        if (hex_common.is_written(regid)):
-            genptr_dst_write_opn(f,regtype, regid, tag)
+    for regtype, regid, toss, numregs in regs:
+        if hex_common.is_written(regid):
+            genptr_dst_write_opn(f, regtype, regid, tag)
 
     f.write("}\n\n")
 
+
 def gen_def_tcg_func(f, tag, tagregs, tagimms):
     regs = tagregs[tag]
     imms = tagimms[tag]
 
     gen_tcg_func(f, tag, regs, imms)
 
+
 def main():
     hex_common.read_semantics_file(sys.argv[1])
     hex_common.read_attribs_file(sys.argv[2])
@@ -607,30 +641,31 @@ def main():
     tagimms = hex_common.get_tagimms()
 
     output_file = sys.argv[-1]
-    with open(output_file, 'w') as f:
+    with open(output_file, "w") as f:
         f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
         f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
         if is_idef_parser_enabled:
-            f.write("#include \"idef-generated-emitter.h.inc\"\n\n")
+            f.write('#include "idef-generated-emitter.h.inc"\n\n')
 
         for tag in hex_common.tags:
             ## Skip the priv instructions
-            if ( "A_PRIV" in hex_common.attribdict[tag] ) :
+            if "A_PRIV" in hex_common.attribdict[tag]:
                 continue
             ## Skip the guest instructions
-            if ( "A_GUEST" in hex_common.attribdict[tag] ) :
+            if "A_GUEST" in hex_common.attribdict[tag]:
                 continue
             ## Skip the diag instructions
-            if ( tag == "Y6_diag" ) :
+            if tag == "Y6_diag":
                 continue
-            if ( tag == "Y6_diag0" ) :
+            if tag == "Y6_diag0":
                 continue
-            if ( tag == "Y6_diag1" ) :
+            if tag == "Y6_diag1":
                 continue
 
             gen_def_tcg_func(f, tag, tagregs, tagimms)
 
         f.write("#endif    /* HEXAGON_TCG_FUNCS_H */\n")
 
+
 if __name__ == "__main__":
     main()
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index bb274d4..502c85a 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -486,30 +486,27 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off,
     }
 }
 
-void gen_set_usr_field(int field, TCGv val)
+void gen_set_usr_field(DisasContext *ctx, int field, TCGv val)
 {
-    tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
-                       val,
+    TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
+    tcg_gen_deposit_tl(usr, usr, val,
                        reg_field_info[field].offset,
                        reg_field_info[field].width);
 }
 
-void gen_set_usr_fieldi(int field, int x)
+void gen_set_usr_fieldi(DisasContext *ctx, int field, int x)
 {
     if (reg_field_info[field].width == 1) {
+        TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
         target_ulong bit = 1 << reg_field_info[field].offset;
         if ((x & 1) == 1) {
-            tcg_gen_ori_tl(hex_new_value[HEX_REG_USR],
-                           hex_new_value[HEX_REG_USR],
-                           bit);
+            tcg_gen_ori_tl(usr, usr, bit);
         } else {
-            tcg_gen_andi_tl(hex_new_value[HEX_REG_USR],
-                            hex_new_value[HEX_REG_USR],
-                            ~bit);
+            tcg_gen_andi_tl(usr, usr, ~bit);
         }
     } else {
         TCGv val = tcg_constant_tl(x);
-        gen_set_usr_field(field, val);
+        gen_set_usr_field(ctx, field, val);
     }
 }
 
@@ -754,7 +751,7 @@ static void gen_endloop0(DisasContext *ctx)
     tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
     {
         tcg_gen_subi_tl(lpcfg, lpcfg, 1);
-        SET_USR_FIELD(USR_LPCFG, lpcfg);
+        gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
     }
     gen_set_label(label2);
 
@@ -829,7 +826,7 @@ static void gen_endloop01(DisasContext *ctx)
     tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
     {
         tcg_gen_subi_tl(lpcfg, lpcfg, 1);
-        SET_USR_FIELD(USR_LPCFG, lpcfg);
+        gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
     }
     gen_set_label(label2);
 
@@ -878,8 +875,9 @@ static void gen_cmpi_jumpnv(DisasContext *ctx,
 }
 
 /* Shift left with saturation */
-static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
+static void gen_shl_sat(DisasContext *ctx, TCGv dst, TCGv src, TCGv shift_amt)
 {
+    TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
     TCGv sh32 = tcg_temp_new();
     TCGv dst_sar = tcg_temp_new();
     TCGv ovf = tcg_temp_new();
@@ -911,7 +909,7 @@ static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
 
     tcg_gen_setcond_tl(TCG_COND_NE, ovf, dst_sar, src);
     tcg_gen_shli_tl(ovf, ovf, reg_field_info[USR_OVF].offset);
-    tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], ovf);
+    tcg_gen_or_tl(usr, usr, ovf);
 
     tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval);
 }
@@ -928,7 +926,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
 }
 
 /* Bidirectional shift right with saturation */
-static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+static void gen_asr_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
 {
     TCGv shift_amt = tcg_temp_new();
     TCGLabel *positive = gen_new_label();
@@ -939,7 +937,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
 
     /* Negative shift amount => shift left */
     tcg_gen_neg_tl(shift_amt, shift_amt);
-    gen_shl_sat(RdV, RsV, shift_amt);
+    gen_shl_sat(ctx, RdV, RsV, shift_amt);
     tcg_gen_br(done);
 
     gen_set_label(positive);
@@ -950,7 +948,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
 }
 
 /* Bidirectional shift left with saturation */
-static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+static void gen_asl_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
 {
     TCGv shift_amt = tcg_temp_new();
     TCGLabel *positive = gen_new_label();
@@ -966,7 +964,7 @@ static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
 
     gen_set_label(positive);
     /* Positive shift amount => shift left */
-    gen_shl_sat(RdV, RsV, shift_amt);
+    gen_shl_sat(ctx, RdV, RsV, shift_amt);
 
     gen_set_label(done);
 }
@@ -1109,20 +1107,19 @@ void probe_noshuf_load(TCGv va, int s, int mi)
  * Note: Since this function might branch, `val` is
  * required to be a `tcg_temp_local`.
  */
-void gen_set_usr_field_if(int field, TCGv val)
+void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val)
 {
     /* Sets the USR field if `val` is non-zero */
     if (reg_field_info[field].width == 1) {
+        TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
         TCGv tmp = tcg_temp_new();
         tcg_gen_extract_tl(tmp, val, 0, reg_field_info[field].width);
         tcg_gen_shli_tl(tmp, tmp, reg_field_info[field].offset);
-        tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
-                      hex_new_value[HEX_REG_USR],
-                      tmp);
+        tcg_gen_or_tl(usr, usr, tmp);
     } else {
         TCGLabel *skip_label = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
-        gen_set_usr_field(field, val);
+        gen_set_usr_field(ctx, field, val);
         gen_set_label(skip_label);
     }
 }
@@ -1190,7 +1187,7 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
 }
 
 /* Implements the fADDSAT64 macro in TCG */
-void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
+void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
 {
     TCGv_i64 sum = tcg_temp_new_i64();
     TCGv_i64 xor = tcg_temp_new_i64();
@@ -1227,7 +1224,7 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
     gen_set_label(ovfl_label);
     tcg_gen_and_i64(cond3, sum, mask);
     tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg);
-    SET_USR_FIELD(USR_OVF, 1);
+    gen_set_usr_fieldi(ctx, USR_OVF, 1);
 
     gen_set_label(ret_label);
 }
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index 591b059..76e497a 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -37,9 +37,9 @@ TCGv gen_read_reg(TCGv result, int num);
 TCGv gen_read_preg(TCGv pred, uint8_t num);
 void gen_log_reg_write(int rnum, TCGv val);
 void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
-void gen_set_usr_field(int field, TCGv val);
-void gen_set_usr_fieldi(int field, int x);
-void gen_set_usr_field_if(int field, TCGv val);
+void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
+void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
+void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
 void gen_sat_i32(TCGv dest, TCGv source, int width);
 void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
 void gen_satu_i32(TCGv dest, TCGv source, int width);
@@ -48,7 +48,7 @@ void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
 void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
 void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
 void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
-void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
+void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
 TCGv gen_8bitsof(TCGv result, TCGv value);
 void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
 TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 368f0b5..ed7f984 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -107,4 +107,4 @@ DEF_HELPER_2(vwhist128qm, void, env, s32)
 DEF_HELPER_4(probe_noshuf_load, void, env, i32, int, int)
 DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int)
 DEF_HELPER_2(probe_hvx_stores, void, env, int)
-DEF_HELPER_3(probe_pkt_scalar_hvx_stores, void, env, int, int)
+DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 0200a66..40f28ca 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -21,14 +21,15 @@ import sys
 import re
 import string
 
-behdict = {}          # tag ->behavior
-semdict = {}          # tag -> semantics
-attribdict = {}       # tag -> attributes
-macros = {}           # macro -> macro information...
-attribinfo = {}       # Register information and misc
-tags = []             # list of all tags
-overrides = {}        # tags with helper overrides
-idef_parser_enabled = {} # tags enabled for idef-parser
+behdict = {}  # tag ->behavior
+semdict = {}  # tag -> semantics
+attribdict = {}  # tag -> attributes
+macros = {}  # macro -> macro information...
+attribinfo = {}  # Register information and misc
+tags = []  # list of all tags
+overrides = {}  # tags with helper overrides
+idef_parser_enabled = {}  # tags enabled for idef-parser
+
 
 # We should do this as a hash for performance,
 # but to keep order let's keep it as a list.
@@ -37,71 +38,77 @@ def uniquify(seq):
     seen_add = seen.add
     return [x for x in seq if x not in seen and not seen_add(x)]
 
-regre = re.compile(
-    r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
+
+regre = re.compile(r"((?<!DUP)[MNORCPQXSGVZA])([stuvwxyzdefg]+)([.]?[LlHh]?)(\d+S?)")
 immre = re.compile(r"[#]([rRsSuUm])(\d+)(?:[:](\d+))?")
-reg_or_immre = \
-    re.compile(r"(((?<!DUP)[MNRCOPQXSGVZA])([stuvwxyzdefg]+)" + \
-                "([.]?[LlHh]?)(\d+S?))|([#]([rRsSuUm])(\d+)[:]?(\d+)?)")
+reg_or_immre = re.compile(
+    r"(((?<!DUP)[MNRCOPQXSGVZA])([stuvwxyzdefg]+)"
+    + "([.]?[LlHh]?)(\d+S?))|([#]([rRsSuUm])(\d+)[:]?(\d+)?)"
+)
 relimmre = re.compile(r"[#]([rR])(\d+)(?:[:](\d+))?")
 absimmre = re.compile(r"[#]([sSuUm])(\d+)(?:[:](\d+))?")
 
 finished_macros = set()
 
-def expand_macro_attribs(macro,allmac_re):
+
+def expand_macro_attribs(macro, allmac_re):
     if macro.key not in finished_macros:
         # Get a list of all things that might be macros
         l = allmac_re.findall(macro.beh)
         for submacro in l:
-            if not submacro: continue
+            if not submacro:
+                continue
             if not macros[submacro]:
-                raise Exception("Couldn't find macro: <%s>" % l)
-            macro.attribs |= expand_macro_attribs(
-                macros[submacro], allmac_re)
+                raise Exception(f"Couldn't find macro: <{l}>")
+            macro.attribs |= expand_macro_attribs(macros[submacro], allmac_re)
             finished_macros.add(macro.key)
     return macro.attribs
 
+
 # When qemu needs an attribute that isn't in the imported files,
 # we'll add it here.
 def add_qemu_macro_attrib(name, attrib):
     macros[name].attribs.add(attrib)
 
-immextre = re.compile(r'f(MUST_)?IMMEXT[(]([UuSsRr])')
+
+immextre = re.compile(r"f(MUST_)?IMMEXT[(]([UuSsRr])")
+
 
 def is_cond_jump(tag):
-    if tag == 'J2_rte':
+    if tag == "J2_rte":
         return False
-    if ('A_HWLOOP0_END' in attribdict[tag] or
-        'A_HWLOOP1_END' in attribdict[tag]):
+    if "A_HWLOOP0_END" in attribdict[tag] or "A_HWLOOP1_END" in attribdict[tag]:
         return False
-    return \
-        re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
+    return re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) != None
+
 
 def is_cond_call(tag):
     return re.compile(r"(if.*fCALL)").search(semdict[tag]) != None
 
+
 def calculate_attribs():
-    add_qemu_macro_attrib('fREAD_PC', 'A_IMPLICIT_READS_PC')
-    add_qemu_macro_attrib('fTRAP', 'A_IMPLICIT_READS_PC')
-    add_qemu_macro_attrib('fWRITE_P0', 'A_WRITES_PRED_REG')
-    add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG')
-    add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG')
-    add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
-    add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
-    add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
-    add_qemu_macro_attrib('fLOAD', 'A_SCALAR_LOAD')
-    add_qemu_macro_attrib('fSTORE', 'A_SCALAR_STORE')
+    add_qemu_macro_attrib("fREAD_PC", "A_IMPLICIT_READS_PC")
+    add_qemu_macro_attrib("fTRAP", "A_IMPLICIT_READS_PC")
+    add_qemu_macro_attrib("fWRITE_P0", "A_WRITES_PRED_REG")
+    add_qemu_macro_attrib("fWRITE_P1", "A_WRITES_PRED_REG")
+    add_qemu_macro_attrib("fWRITE_P2", "A_WRITES_PRED_REG")
+    add_qemu_macro_attrib("fWRITE_P3", "A_WRITES_PRED_REG")
+    add_qemu_macro_attrib("fSET_OVERFLOW", "A_IMPLICIT_WRITES_USR")
+    add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
+    add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
+    add_qemu_macro_attrib("fSTORE", "A_SCALAR_STORE")
 
     # Recurse down macros, find attributes from sub-macros
     macroValues = list(macros.values())
-    allmacros_restr = "|".join(set([ m.re.pattern for m in macroValues ]))
+    allmacros_restr = "|".join(set([m.re.pattern for m in macroValues]))
     allmacros_re = re.compile(allmacros_restr)
     for macro in macroValues:
-        expand_macro_attribs(macro,allmacros_re)
+        expand_macro_attribs(macro, allmacros_re)
     # Append attributes to all instructions
     for tag in tags:
         for macname in allmacros_re.findall(semdict[tag]):
-            if not macname: continue
+            if not macname:
+                continue
             macro = macros[macname]
             attribdict[tag] |= set(macro.attribs)
     # Figure out which instructions write predicate registers
@@ -110,31 +117,34 @@ def calculate_attribs():
         regs = tagregs[tag]
         for regtype, regid, toss, numregs in regs:
             if regtype == "P" and is_written(regid):
-                attribdict[tag].add('A_WRITES_PRED_REG')
+                attribdict[tag].add("A_WRITES_PRED_REG")
     # Mark conditional jumps and calls
     #     Not all instructions are properly marked with A_CONDEXEC
     for tag in tags:
         if is_cond_jump(tag) or is_cond_call(tag):
-            attribdict[tag].add('A_CONDEXEC')
+            attribdict[tag].add("A_CONDEXEC")
+
 
 def SEMANTICS(tag, beh, sem):
-    #print tag,beh,sem
+    # print tag,beh,sem
     behdict[tag] = beh
     semdict[tag] = sem
     attribdict[tag] = set()
-    tags.append(tag)        # dicts have no order, this is for order
+    tags.append(tag)  # dicts have no order, this is for order
+
 
 def ATTRIBUTES(tag, attribstring):
-    attribstring = \
-        attribstring.replace("ATTRIBS","").replace("(","").replace(")","")
+    attribstring = attribstring.replace("ATTRIBS", "").replace("(", "").replace(")", "")
     if not attribstring:
         return
     attribs = attribstring.split(",")
     for attrib in attribs:
         attribdict[tag].add(attrib.strip())
 
+
 class Macro(object):
-    __slots__ = ['key','name', 'beh', 'attribs', 're']
+    __slots__ = ["key", "name", "beh", "attribs", "re"]
+
     def __init__(self, name, beh, attribs):
         self.key = name
         self.name = name
@@ -142,20 +152,24 @@ class Macro(object):
         self.attribs = set(attribs)
         self.re = re.compile("\\b" + name + "\\b")
 
-def MACROATTRIB(macname,beh,attribstring):
-    attribstring = attribstring.replace("(","").replace(")","")
+
+def MACROATTRIB(macname, beh, attribstring):
+    attribstring = attribstring.replace("(", "").replace(")", "")
     if attribstring:
         attribs = attribstring.split(",")
     else:
         attribs = []
-    macros[macname] = Macro(macname,beh,attribs)
+    macros[macname] = Macro(macname, beh, attribs)
+
 
 def compute_tag_regs(tag):
     return uniquify(regre.findall(behdict[tag]))
 
+
 def compute_tag_immediates(tag):
     return uniquify(immre.findall(behdict[tag]))
 
+
 ##
 ##  tagregs is the main data structure we'll use
 ##  tagregs[tag] will contain the registers used by an instruction
@@ -180,89 +194,113 @@ def compute_tag_immediates(tag):
 def get_tagregs():
     return dict(zip(tags, list(map(compute_tag_regs, tags))))
 
+
 def get_tagimms():
     return dict(zip(tags, list(map(compute_tag_immediates, tags))))
 
+
 def is_pair(regid):
     return len(regid) == 2
 
+
 def is_single(regid):
     return len(regid) == 1
 
+
 def is_written(regid):
     return regid[0] in "dexy"
 
+
 def is_writeonly(regid):
     return regid[0] in "de"
 
+
 def is_read(regid):
     return regid[0] in "stuvwxy"
 
+
 def is_readwrite(regid):
     return regid[0] in "xy"
 
+
 def is_scalar_reg(regtype):
     return regtype in "RPC"
 
+
 def is_hvx_reg(regtype):
     return regtype in "VQ"
 
+
 def is_old_val(regtype, regid, tag):
-    return regtype+regid+'V' in semdict[tag]
+    return regtype + regid + "V" in semdict[tag]
+
 
 def is_new_val(regtype, regid, tag):
-    return regtype+regid+'N' in semdict[tag]
+    return regtype + regid + "N" in semdict[tag]
+
 
 def need_slot(tag):
-    if (('A_CONDEXEC' in attribdict[tag] and
-         'A_JUMP' not in attribdict[tag]) or
-        'A_STORE' in attribdict[tag] or
-        'A_LOAD' in attribdict[tag]):
+    if (
+        ("A_CONDEXEC" in attribdict[tag] and "A_JUMP" not in attribdict[tag])
+        or "A_STORE" in attribdict[tag]
+        or "A_LOAD" in attribdict[tag]
+    ):
         return 1
     else:
         return 0
 
+
 def need_part1(tag):
     return re.compile(r"fPART1").search(semdict[tag])
 
+
 def need_ea(tag):
     return re.compile(r"\bEA\b").search(semdict[tag])
 
+
 def need_PC(tag):
-    return 'A_IMPLICIT_READS_PC' in attribdict[tag]
+    return "A_IMPLICIT_READS_PC" in attribdict[tag]
+
 
 def helper_needs_next_PC(tag):
-    return 'A_CALL' in attribdict[tag]
+    return "A_CALL" in attribdict[tag]
+
 
 def need_pkt_has_multi_cof(tag):
-    return 'A_COF' in attribdict[tag]
+    return "A_COF" in attribdict[tag]
+
 
 def need_condexec_reg(tag, regs):
-    if 'A_CONDEXEC' in attribdict[tag]:
+    if "A_CONDEXEC" in attribdict[tag]:
         for regtype, regid, toss, numregs in regs:
             if is_writeonly(regid) and not is_hvx_reg(regtype):
                 return True
     return False
 
+
 def skip_qemu_helper(tag):
     return tag in overrides.keys()
 
+
 def is_tmp_result(tag):
-    return ('A_CVI_TMP' in attribdict[tag] or
-            'A_CVI_TMP_DST' in attribdict[tag])
+    return "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in attribdict[tag]
+
 
 def is_new_result(tag):
-    return ('A_CVI_NEW' in attribdict[tag])
+    return "A_CVI_NEW" in attribdict[tag]
+
 
 def is_idef_parser_enabled(tag):
     return tag in idef_parser_enabled
 
+
 def imm_name(immlett):
-    return "%siV" % immlett
+    return f"{immlett}iV"
+
 
 def read_semantics_file(name):
     eval_line = ""
-    for line in open(name, 'rt').readlines():
+    for line in open(name, "rt").readlines():
         if not line.startswith("#"):
             eval_line += line
             if line.endswith("\\\n"):
@@ -271,24 +309,29 @@ def read_semantics_file(name):
                 eval(eval_line.strip())
                 eval_line = ""
 
+
 def read_attribs_file(name):
-    attribre = re.compile(r'DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), ' +
-            r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)')
-    for line in open(name, 'rt').readlines():
+    attribre = re.compile(
+        r"DEF_ATTRIB\(([A-Za-z0-9_]+), ([^,]*), "
+        + r'"([A-Za-z0-9_\.]*)", "([A-Za-z0-9_\.]*)"\)'
+    )
+    for line in open(name, "rt").readlines():
         if not attribre.match(line):
             continue
-        (attrib_base,descr,rreg,wreg) = attribre.findall(line)[0]
-        attrib_base = 'A_' + attrib_base
-        attribinfo[attrib_base] = {'rreg':rreg, 'wreg':wreg, 'descr':descr}
+        (attrib_base, descr, rreg, wreg) = attribre.findall(line)[0]
+        attrib_base = "A_" + attrib_base
+        attribinfo[attrib_base] = {"rreg": rreg, "wreg": wreg, "descr": descr}
+
 
 def read_overrides_file(name):
     overridere = re.compile("#define fGEN_TCG_([A-Za-z0-9_]+)\(.*")
-    for line in open(name, 'rt').readlines():
+    for line in open(name, "rt").readlines():
         if not overridere.match(line):
             continue
         tag = overridere.findall(line)[0]
         overrides[tag] = True
 
+
 def read_idef_parser_enabled_file(name):
     global idef_parser_enabled
     with open(name, "r") as idef_parser_enabled_file:
diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y
index 7d05773..5444fd4 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -362,7 +362,7 @@ assign_statement : lvalue '=' rvalue
                                 "Assignment side-effect not modeled!");
                        $3 = gen_rvalue_truncate(c, &@1, &$3);
                        $3 = rvalue_materialize(c, &@1, &$3);
-                       OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n");
+                       OUT(c, &@1, "gen_set_usr_field(ctx, USR_LPCFG, ", &$3, ");\n");
                    }
                  | DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')'
                    {
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 18cde6a..86511ef 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1640,7 +1640,8 @@ void gen_addsat64(Context *c,
 {
     HexValue op1_m = rvalue_materialize(c, locp, op1);
     HexValue op2_m = rvalue_materialize(c, locp, op2);
-    OUT(c, locp, "gen_add_sat_i64(", dst, ", ", &op1_m, ", ", &op2_m, ");\n");
+    OUT(c, locp, "gen_add_sat_i64(ctx, ", dst, ", ", &op1_m, ", ",
+                                  &op2_m, ");\n");
 }
 
 void gen_inst(Context *c, GString *iname)
@@ -1971,7 +1972,7 @@ HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat *sat,
     OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "_ovfl(");
     OUT(c, locp, &ovfl, ", ", &res, ", ", value, ", ", &width->imm.value,
         ");\n");
-    OUT(c, locp, "gen_set_usr_field_if(USR_OVF,", &ovfl, ");\n");
+    OUT(c, locp, "gen_set_usr_field_if(ctx, USR_OVF,", &ovfl, ");\n");
 
     return res;
 }
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 482a9c7..3e162de 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -22,16 +22,6 @@
 #include "hex_regs.h"
 #include "reg_fields.h"
 
-#ifdef QEMU_GENERATE
-#define READ_REG(dest, NUM)              gen_read_reg(dest, NUM)
-#else
-#define READ_REG(NUM)                    (env->gpr[(NUM)])
-#define READ_PREG(NUM)                   (env->pred[NUM])
-
-#define WRITE_RREG(NUM, VAL)             log_reg_write(env, NUM, VAL, slot)
-#define WRITE_PREG(NUM, VAL)             log_pred_write(env, NUM, VAL)
-#endif
-
 #define PCALIGN 4
 #define PCALIGN_MASK (PCALIGN - 1)
 
@@ -48,14 +38,6 @@
 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
-
-#define SET_USR_FIELD_FUNC(X) \
-    __builtin_choose_expr(TYPE_INT(X), \
-        gen_set_usr_fieldi, \
-        __builtin_choose_expr(TYPE_TCGV(X), \
-            gen_set_usr_field, (void)0))
-#define SET_USR_FIELD(FIELD, VAL) \
-    SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
 #else
 #define GET_USR_FIELD(FIELD) \
     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
@@ -361,37 +343,30 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
     tcg_gen_shli_tl(result, result, shift);
     return result;
 }
-#define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
-#else
-#define fREAD_IREG(VAL) \
-    (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
 #endif
 
-#define fREAD_LR() (READ_REG(HEX_REG_LR))
+#define fREAD_LR() (env->gpr[HEX_REG_LR])
 
-#define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
-#define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
-#define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
+#define fWRITE_LR(A) log_reg_write(env, HEX_REG_LR, A)
+#define fWRITE_FP(A) log_reg_write(env, HEX_REG_FP, A)
+#define fWRITE_SP(A) log_reg_write(env, HEX_REG_SP, A)
 
-#define fREAD_SP() (READ_REG(HEX_REG_SP))
-#define fREAD_LC0 (READ_REG(HEX_REG_LC0))
-#define fREAD_LC1 (READ_REG(HEX_REG_LC1))
-#define fREAD_SA0 (READ_REG(HEX_REG_SA0))
-#define fREAD_SA1 (READ_REG(HEX_REG_SA1))
-#define fREAD_FP() (READ_REG(HEX_REG_FP))
+#define fREAD_SP() (env->gpr[HEX_REG_SP])
+#define fREAD_LC0 (env->gpr[HEX_REG_LC0])
+#define fREAD_LC1 (env->gpr[HEX_REG_LC1])
+#define fREAD_SA0 (env->gpr[HEX_REG_SA0])
+#define fREAD_SA1 (env->gpr[HEX_REG_SA1])
+#define fREAD_FP() (env->gpr[HEX_REG_FP])
 #ifdef FIXME
 /* Figure out how to get insn->extension_valid to helper */
 #define fREAD_GP() \
-    (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
+    (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
 #else
-#define fREAD_GP() READ_REG(HEX_REG_GP)
+#define fREAD_GP() (env->gpr[HEX_REG_GP])
 #endif
 #define fREAD_PC() (PC)
 
-#define fREAD_NPC() (next_PC & (0xfffffffe))
-
-#define fREAD_P0() (READ_PREG(0))
-#define fREAD_P3() (READ_PREG(3))
+#define fREAD_P0() (env->pred[0])
 
 #define fCHECK_PCALIGN(A)
 
@@ -402,24 +377,22 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 #define fWRITE_LOOP_REGS0(START, COUNT) \
     do { \
-        WRITE_RREG(HEX_REG_LC0, COUNT);  \
-        WRITE_RREG(HEX_REG_SA0, START); \
+        log_reg_write(env, HEX_REG_LC0, COUNT);  \
+        log_reg_write(env, HEX_REG_SA0, START); \
     } while (0)
 #define fWRITE_LOOP_REGS1(START, COUNT) \
     do { \
-        WRITE_RREG(HEX_REG_LC1, COUNT);  \
-        WRITE_RREG(HEX_REG_SA1, START);\
+        log_reg_write(env, HEX_REG_LC1, COUNT);  \
+        log_reg_write(env, HEX_REG_SA1, START);\
     } while (0)
-#define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
-#define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 
 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
-#define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
-#define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
-#define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
-#define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
+#define fWRITE_P0(VAL) log_pred_write(env, 0, VAL)
+#define fWRITE_P1(VAL) log_pred_write(env, 1, VAL)
+#define fWRITE_P2(VAL) log_pred_write(env, 2, VAL)
+#define fWRITE_P3(VAL) log_pred_write(env, 3, VAL)
 #define fPART1(WORK) if (part1) { WORK; return; }
 #define fCAST4u(A) ((uint32_t)(A))
 #define fCAST4s(A) ((int32_t)(A))
@@ -576,7 +549,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 
 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 
-#define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
+#define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 
@@ -686,22 +659,10 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
                    reg_field_info[FIELD].width, \
                    reg_field_info[FIELD].offset)
-#define fGET_FIELD(VAL, FIELD)
-#define fSET_FIELD(VAL, FIELD, NEWVAL)
-#define fBARRIER()
-#define fSYNCH()
-#define fISYNC()
-#define fDCFETCH(REG) \
-    do { (void)REG; } while (0) /* Nothing to do in qemu */
-#define fICINVA(REG) \
-    do { (void)REG; } while (0) /* Nothing to do in qemu */
-#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
-#define fDCCLEANA(REG) \
-    do { (void)REG; } while (0) /* Nothing to do in qemu */
-#define fDCCLEANINVA(REG) \
-    do { (void)REG; } while (0) /* Nothing to do in qemu */
-
-#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
+
+#ifdef QEMU_GENERATE
+#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG))
+#endif
 
 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
                                 STRBITNUM) /* Nothing */
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index c9a1560..3cc71b6 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -53,7 +53,7 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp)
 }
 
 void log_reg_write(CPUHexagonState *env, int rnum,
-                   target_ulong val, uint32_t slot)
+                   target_ulong val)
 {
     HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")",
                   rnum, val, val);
@@ -488,8 +488,7 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
     }
 }
 
-void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask,
-                                         int mmu_idx)
+void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
 {
     bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0);
     bool has_st1 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1);
@@ -497,6 +496,7 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask,
         FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES);
     bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED);
     bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED);
+    int mmu_idx = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX);
 
     if (has_st0) {
         probe_store(env, 0, mmu_idx, s0_is_pred);
diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h
index 34b3a53..db22b54 100644
--- a/target/hexagon/op_helper.h
+++ b/target/hexagon/op_helper.h
@@ -27,7 +27,7 @@ uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
 uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
 
 void log_reg_write(CPUHexagonState *env, int rnum,
-                   target_ulong val, uint32_t slot);
+                   target_ulong val);
 void log_store64(CPUHexagonState *env, target_ulong addr,
                  int64_t val, int width, int slot);
 void log_store32(CPUHexagonState *env, target_ulong addr,
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 665476a..c087f18 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -128,14 +128,19 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
     return translator_use_goto_tb(&ctx->base, dest);
 }
 
-static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool
+                        move_to_pc)
 {
     if (use_goto_tb(ctx, dest)) {
         tcg_gen_goto_tb(idx);
-        tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
+        if (move_to_pc) {
+            tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
+        }
         tcg_gen_exit_tb(ctx->base.tb, idx);
     } else {
-        tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
+        if (move_to_pc) {
+            tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
+        }
         tcg_gen_lookup_and_goto_ptr();
     }
 }
@@ -150,11 +155,11 @@ static void gen_end_tb(DisasContext *ctx)
         if (ctx->branch_cond != TCG_COND_ALWAYS) {
             TCGLabel *skip = gen_new_label();
             tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip);
-            gen_goto_tb(ctx, 0, ctx->branch_dest);
+            gen_goto_tb(ctx, 0, ctx->branch_dest, true);
             gen_set_label(skip);
-            gen_goto_tb(ctx, 1, ctx->next_PC);
+            gen_goto_tb(ctx, 1, ctx->next_PC, false);
         } else {
-            gen_goto_tb(ctx, 0, ctx->branch_dest);
+            gen_goto_tb(ctx, 0, ctx->branch_dest, true);
         }
     } else if (ctx->is_tight_loop &&
                pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) {
@@ -165,9 +170,9 @@ static void gen_end_tb(DisasContext *ctx)
         TCGLabel *skip = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, skip);
         tcg_gen_subi_tl(hex_gpr[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], 1);
-        gen_goto_tb(ctx, 0, ctx->base.tb->pc);
+        gen_goto_tb(ctx, 0, ctx->base.tb->pc, true);
         gen_set_label(skip);
-        gen_goto_tb(ctx, 1, ctx->next_PC);
+        gen_goto_tb(ctx, 1, ctx->next_PC, false);
     } else {
         tcg_gen_lookup_and_goto_ptr();
     }
@@ -803,13 +808,11 @@ static void gen_commit_packet(DisasContext *ctx)
         g_assert(!has_store_s1 && !has_hvx_store);
         process_dczeroa(ctx);
     } else if (has_hvx_store) {
-        TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
-
         if (!has_store_s0 && !has_store_s1) {
+            TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
             gen_helper_probe_hvx_stores(cpu_env, mem_idx);
         } else {
             int mask = 0;
-            TCGv mask_tcgv;
 
             if (has_store_s0) {
                 mask =
@@ -834,8 +837,10 @@ static void gen_commit_packet(DisasContext *ctx)
                     FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
                                S1_IS_PRED, 1);
             }
-            mask_tcgv = tcg_constant_tl(mask);
-            gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx);
+            mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,
+                              ctx->mem_idx);
+            gen_helper_probe_pkt_scalar_hvx_stores(cpu_env,
+                                                   tcg_constant_tl(mask));
         }
     } else if (has_store_s0 && has_store_s1) {
         /*
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index db832b0..4b9f21c 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -178,5 +178,6 @@ FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1,        1, 1)
 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,     3, 1)
 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED,     4, 1)
+FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,        5, 2)
 
 #endif