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| author | Hongren (Zenithal) Zheng <i@zenithal.me> | 2022-05-18 20:46:58 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | 5160bacc0638088a7cb0180d2be3d8c2c8a21831 (patch) | |
| tree | f4ba73b24ec68d81f9fb05bbedca7b15d39352c2 /target | |
| parent | d644e5e44ff627d6b4da73a65795f60335ba4cb9 (diff) | |
| download | qemu-5160bacc0638088a7cb0180d2be3d8c2c8a21831.zip qemu-5160bacc0638088a7cb0180d2be3d8c2c8a21831.tar.gz qemu-5160bacc0638088a7cb0180d2be3d8c2c8a21831.tar.bz2 | |
target/riscv: add zicsr/zifencei to isa_string
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce1c257..a91253d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1029,6 +1029,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) * extensions by an underscore. */ struct isa_ext_data isa_edata_arr[] = { + ISA_EDATA_ENTRY(zicsr, ext_icsr), + ISA_EDATA_ENTRY(zifencei, ext_ifencei), ISA_EDATA_ENTRY(zfh, ext_zfh), ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), ISA_EDATA_ENTRY(zfinx, ext_zfinx), |