diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-27 11:18:25 -0700 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-30 17:05:09 +0100 |
commit | 3a40518079ff295b560b9ee193768e57a25007e2 (patch) | |
tree | 76343f1ad0aff4b4ed64f5ac422887beb4eaf722 /target | |
parent | c437c59ba1842dc8488316412cb071d57d8231d8 (diff) | |
download | qemu-3a40518079ff295b560b9ee193768e57a25007e2.zip qemu-3a40518079ff295b560b9ee193768e57a25007e2.tar.gz qemu-3a40518079ff295b560b9ee193768e57a25007e2.tar.bz2 |
target/arm: Reject add/sub w/ shifted byte early
Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
and do_zzi_sat which are intended to reject an 8-bit shift of an
8-bit constant for 8-bit element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/arm/sve.decode | 35 | ||||
-rw-r--r-- | target/arm/translate-sve.c | 9 |
2 files changed, 28 insertions, 16 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index c02da0a..8cff63c 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -793,13 +793,34 @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 } # SVE integer add/subtract immediate (unpredicated) -ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u -SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u -SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u -SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u -UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u -SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u -UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u +{ + INVALID 00100101 00 100 000 11 1 -------- ----- + ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u +} +{ + INVALID 00100101 00 100 001 11 1 -------- ----- + SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u +} +{ + INVALID 00100101 00 100 011 11 1 -------- ----- + SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u +} +{ + INVALID 00100101 00 100 100 11 1 -------- ----- + SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u +} +{ + INVALID 00100101 00 100 101 11 1 -------- ----- + UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u +} +{ + INVALID 00100101 00 100 110 11 1 -------- ----- + SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u +} +{ + INVALID 00100101 00 100 111 11 1 -------- ----- + UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u +} # SVE integer min/max immediate (unpredicated) SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 14faef0..bf988ca 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3262,9 +3262,6 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a) { - if (a->esz == 0 && extract32(s->insn, 13, 1)) { - return false; - } return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a); } @@ -3305,9 +3302,6 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) .scalar_first = true } }; - if (a->esz == 0 && extract32(s->insn, 13, 1)) { - return false; - } if (sve_access_check(s)) { unsigned vsz = vec_full_reg_size(s); tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), @@ -3321,9 +3315,6 @@ TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a) static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) { - if (a->esz == 0 && extract32(s->insn, 13, 1)) { - return false; - } if (sve_access_check(s)) { do_sat_addsub_vec(s, a->esz, a->rd, a->rn, tcg_constant_i64(a->imm), u, d); |