diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2022-05-11 20:15:22 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | 24826da0eeacb27a5da6be764c8e853b2cede25b (patch) | |
| tree | a4a76c1553a23335db33ac3bd65d4055af4ce517 /target | |
| parent | c1fbcecb3a97ecce2cde5052319df34ca6bcc988 (diff) | |
| download | qemu-24826da0eeacb27a5da6be764c8e853b2cede25b.zip qemu-24826da0eeacb27a5da6be764c8e853b2cede25b.tar.gz qemu-24826da0eeacb27a5da6be764c8e853b2cede25b.tar.bz2 | |
target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_helper.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1aa4f2..b16bfe0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1367,7 +1367,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: - write_gva = true; + write_gva = env->two_stage_lookup; tval = env->badaddr; break; case RISCV_EXCP_ILLEGAL_INST: @@ -1434,7 +1434,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trap into HS mode */ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); htval = env->guest_phys_fault_addr; - write_gva = false; } env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); } |