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authorBin Meng <bmeng@tinylab.org>2022-12-07 17:00:37 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-01-06 10:42:55 +1000
commit0ff430a5b10db884d6dd6cde930b4e73283b7507 (patch)
tree65ae7573480dd1c3171cb445b7cdcddf31ae92fe /target
parent2bfec53b4c7d5e5ddd08ea6ef77257cba612700d (diff)
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target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when leaving M-mode. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221207090037.281452-2-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/op_helper.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index a047d38..878bcb0 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -154,6 +154,9 @@ target_ulong helper_sret(CPURISCVState *env)
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+ if (env->priv_ver >= PRIV_VERSION_1_12_0) {
+ mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
+ }
env->mstatus = mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -203,6 +206,9 @@ target_ulong helper_mret(CPURISCVState *env)
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
+ if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
+ mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
+ }
env->mstatus = mstatus;
riscv_cpu_set_mode(env, prev_priv);