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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-11-09 15:19:17 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-13 13:15:31 +0000 |
| commit | fc58891d0422607d172a3d6b3158798f2556aef1 (patch) | |
| tree | bd8a9831208b3ab2d75c7824bd364aa8f441bec2 /target | |
| parent | 1d675e59ea194fc918fe0f553eb79209b3fb3a8f (diff) | |
| download | qemu-fc58891d0422607d172a3d6b3158798f2556aef1.zip qemu-fc58891d0422607d172a3d6b3158798f2556aef1.tar.gz qemu-fc58891d0422607d172a3d6b3158798f2556aef1.tar.bz2 | |
target/arm: HVC at EL3 should go to EL3, not EL2
AArch64 permits code at EL3 to use the HVC instruction; however the
exception we take should go to EL3, not down to EL2 (see the pseudocode
AArch64.CallHypervisor()). Fix the target EL.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20231109151917.1925107-1-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 41484d8..a2e49c3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2351,6 +2351,8 @@ static bool trans_SVC(DisasContext *s, arg_i *a) static bool trans_HVC(DisasContext *s, arg_i *a) { + int target_el = s->current_el == 3 ? 3 : 2; + if (s->current_el == 0) { unallocated_encoding(s); return true; @@ -2363,7 +2365,7 @@ static bool trans_HVC(DisasContext *s, arg_i *a) gen_helper_pre_hvc(tcg_env); /* Architecture requires ss advance before we do the actual work */ gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), target_el); return true; } |