diff options
| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 12:18:09 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-09-06 08:06:47 -0700 |
| commit | f62bd897e64c6fb1f93e8795e835980516fe53b5 (patch) | |
| tree | 5d8d5efd0161209f539c27f93fc6b6a3d6e1e25d /target | |
| parent | b14768544fd715a3f1742c10fc36ae81c703cbc1 (diff) | |
| download | qemu-f62bd897e64c6fb1f93e8795e835980516fe53b5.zip qemu-f62bd897e64c6fb1f93e8795e835980516fe53b5.tar.gz qemu-f62bd897e64c6fb1f93e8795e835980516fe53b5.tar.bz2 | |
target/arm: [tcg] Port to insn_start
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 3138a23..0051572 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11936,6 +11936,16 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11979,10 +11989,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + arm_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; |