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author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2017-03-04 15:56:50 -0300 |
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committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-03-20 11:06:32 +0000 |
commit | 965447eecb6b98d6dfc4dbd97f836093c7e398a0 (patch) | |
tree | f957d6a6994f71b8b00f71c026e07712db5204b6 /target | |
parent | 989f2aa9af7f05c323761b66c0e299059a19b7b1 (diff) | |
download | qemu-965447eecb6b98d6dfc4dbd97f836093c7e398a0.zip qemu-965447eecb6b98d6dfc4dbd97f836093c7e398a0.tar.gz qemu-965447eecb6b98d6dfc4dbd97f836093c7e398a0.tar.bz2 |
target-mips: log bad coprocessor0 register accesses with LOG_UNIMP
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/mips/translate.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 1fe0ff3..5c030a9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4872,7 +4872,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) return; cp0_unimplemented: - LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel); + qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel); tcg_gen_movi_tl(arg, 0); } @@ -4944,7 +4944,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) (void)rn; /* avoid a compiler warning */ cp0_unimplemented: - LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel); + qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel); } static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) @@ -5627,7 +5627,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) return; cp0_unimplemented: - LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); + qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel); gen_mfc0_unimplemented(ctx, arg); } @@ -6294,7 +6294,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) return; cp0_unimplemented: - LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); + qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel); } #if defined(TARGET_MIPS64) @@ -6928,7 +6928,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) return; cp0_unimplemented: - LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); + qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); gen_mfc0_unimplemented(ctx, arg); } @@ -7593,7 +7593,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) return; cp0_unimplemented: - LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); + qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); } #endif /* TARGET_MIPS64 */ |