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authorYongbok Kim <yongbok.kim@mips.com>2018-08-02 16:16:18 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2018-08-24 17:51:59 +0200
commit642241870a029da1525ad1641e1c99d434580817 (patch)
treea480fe2c6e043c8d0db1be51e17a46e0c19a58b3 /target
parente0cf0e6586d6a2c7e56b58bdfb5a67cec04c2999 (diff)
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target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
Add emulation of misc nanoMIPS instructions situated in pool32axf. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'target')
-rw-r--r--target/mips/translate.c91
1 files changed, 91 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 429ad23..c26ea68 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17034,6 +17034,89 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
}
}
+static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
+{
+#ifndef CONFIG_USER_ONLY
+ int rt = extract32(ctx->opcode, 21, 5);
+ int rs = extract32(ctx->opcode, 16, 5);
+#endif
+
+ switch (extract32(ctx->opcode, 6, 3)) {
+ case NM_POOL32AXF_4:
+ case NM_POOL32AXF_5:
+ switch (extract32(ctx->opcode, 9, 7)) {
+#ifndef CONFIG_USER_ONLY
+ case NM_TLBP:
+ gen_cp0(env, ctx, OPC_TLBP, 0, 0);
+ break;
+ case NM_TLBR:
+ gen_cp0(env, ctx, OPC_TLBR, 0, 0);
+ break;
+ case NM_TLBWI:
+ gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
+ break;
+ case NM_TLBWR:
+ gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
+ break;
+ case NM_TLBINV:
+ gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
+ break;
+ case NM_TLBINVF:
+ gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
+ break;
+ case NM_DI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_di(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_EI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_ei(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_RDPGPR:
+ gen_load_srsgpr(rs, rt);
+ break;
+ case NM_WRPGPR:
+ gen_store_srsgpr(rs, rt);
+ break;
+ case NM_WAIT:
+ gen_cp0(env, ctx, OPC_WAIT, 0, 0);
+ break;
+ case NM_DERET:
+ gen_cp0(env, ctx, OPC_DERET, 0, 0);
+ break;
+ case NM_ERETX:
+ gen_cp0(env, ctx, OPC_ERET, 0, 0);
+ break;
+#endif
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -17404,6 +17487,14 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_pool32a0_nanomips_insn(ctx);
break;
case NM_POOL32A7:
+ switch (extract32(ctx->opcode, 3, 3)) {
+ case NM_POOL32AXF:
+ gen_pool32axf_nanomips_insn(env, ctx);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);