diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-03-15 12:46:04 -0600 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-05-04 11:41:24 +1000 |
| commit | 56ced49760df758650e852361b1b1a359ca6c904 (patch) | |
| tree | 7aacf0e9a9c65f1313db08f1ea48ea079ac55954 /target | |
| parent | f7a7b6525c5b5f06553582d8617052bf43678984 (diff) | |
| download | qemu-56ced49760df758650e852361b1b1a359ca6c904.zip qemu-56ced49760df758650e852361b1b1a359ca6c904.tar.gz qemu-56ced49760df758650e852361b1b1a359ca6c904.tar.bz2 | |
target/ppc: Fix comment for MSR_FE{0,1}
As per hreg_compute_hflags:
We 'forget' FE0 & FE1: we'll never generate imprecise exceptions
remove the hflags marker from the respective comments.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-7-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 79c4033..fd13489 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -322,13 +322,13 @@ typedef struct ppc_v3_pate_t { #define MSR_PR 14 /* Problem state hflags */ #define MSR_FP 13 /* Floating point available hflags */ #define MSR_ME 12 /* Machine check interrupt enable */ -#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ +#define MSR_FE0 11 /* Floating point exception mode 0 */ #define MSR_SE 10 /* Single-step trace enable x hflags */ #define MSR_DWE 10 /* Debug wait enable on 405 x */ #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ #define MSR_BE 9 /* Branch trace enable x hflags */ #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ -#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ +#define MSR_FE1 8 /* Floating point exception mode 1 */ #define MSR_AL 7 /* AL bit on POWER */ #define MSR_EP 6 /* Exception prefix on 601 */ #define MSR_IR 5 /* Instruction relocate */ |