diff options
| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 12:30:16 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-09-06 08:06:47 -0700 |
| commit | 0cb56b373da70047979b61b042f59aaff4012e1b (patch) | |
| tree | 7d6c10d3a19821e2d34d94fda8051f6ae878ad06 /target | |
| parent | a68956ad7f8510bdc0b54793c65c62c6a94570a4 (diff) | |
| download | qemu-0cb56b373da70047979b61b042f59aaff4012e1b.zip qemu-0cb56b373da70047979b61b042f59aaff4012e1b.tar.gz qemu-0cb56b373da70047979b61b042f59aaff4012e1b.tar.bz2 | |
target/arm: [tcg,a64] Port to breakpoint_check
Incrementally paves the way towards using the generic instruction translation
loop.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan>
[rth: Use DISAS_TOO_MANY for "execute only one more" after bp.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-a64.c | 48 |
1 files changed, 31 insertions, 17 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1eab106..e941982 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11267,6 +11267,30 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc += 4; + dc->base.is_jmp = DISAS_NORETURN; + } + + return true; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11303,25 +11327,15 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp = DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc + dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. */ - dc->pc += 4; - goto done_generating; + if (bp->pc == dc->base.pc_next) { + if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) { @@ -11392,6 +11406,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -11429,7 +11444,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, } } -done_generating: gen_tb_end(tb, dc->base.num_insns); #ifdef DEBUG_DISAS |