diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:30:28 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-05 13:23:03 +0100 |
| commit | beb595f657d615856fee904f1e0f74f5e1e299a3 (patch) | |
| tree | 55b332de04c8a6178f22b37eba5dc54aaacc3435 /target | |
| parent | 48c04a5dfaf2c08e00b659a22c502ec098999cf1 (diff) | |
| download | qemu-beb595f657d615856fee904f1e0f74f5e1e299a3.zip qemu-beb595f657d615856fee904f1e0f74f5e1e299a3.tar.gz qemu-beb595f657d615856fee904f1e0f74f5e1e299a3.tar.bz2 | |
target/arm: Convert PLI, PLD, PLDW
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-39-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/a32-uncond.decode | 10 | ||||
| -rw-r--r-- | target/arm/translate.c | 37 |
2 files changed, 30 insertions, 17 deletions
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 32253b4..ddc5edf 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 diff --git a/target/arm/translate.c b/target/arm/translate.c index a599da9..3f02532 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10253,6 +10253,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a) } /* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + +/* * Legacy decoder. */ @@ -10312,23 +10332,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f30f000) == 0x0510f000) || - ((insn & 0x0f30f010) == 0x0710f000)) { - if ((insn & (1 << 22)) == 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) == 0x0450f000) || - ((insn & 0x0f70f010) == 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) == 0x04100000) || ((insn & 0x0f700010) == 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { |