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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-15 14:57:14 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-15 15:23:34 +0100 |
| commit | 792a557847697235037fea30eaaacb9b45b4c9e5 (patch) | |
| tree | 8198b433d6bd0bcdc05d789fd24f6cc59ea22d73 /target | |
| parent | ef23cb726dc32375bc2fca7ac3e9f34816f6ee13 (diff) | |
| download | qemu-792a557847697235037fea30eaaacb9b45b4c9e5.zip qemu-792a557847697235037fea30eaaacb9b45b4c9e5.tar.gz qemu-792a557847697235037fea30eaaacb9b45b4c9e5.tar.bz2 | |
target/arm: Implement SVE copy to vector (predicated)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/sve.decode | 6 | ||||
| -rw-r--r-- | target/arm/translate-sve.c | 19 |
2 files changed, 25 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 1226867..519139f 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -450,6 +450,12 @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn +# SVE copy element from SIMD&FP scalar register +CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn + +# SVE copy element from general register to vector (predicated) +CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn + ### SVE Predicate Logical Operations Group # SVE predicate logical operations diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index feb4c09..eed5952 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2624,6 +2624,25 @@ static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) return do_last_general(s, a, true); } +static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); + } + return true; +} + +static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + if (sve_access_check(s)) { + int ofs = vec_reg_offset(s, a->rn, 0, a->esz); + TCGv_i64 t = load_esz(cpu_env, ofs, a->esz); + do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); + tcg_temp_free_i64(t); + } + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ |