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| author | Michael Clark <mjc@sifive.com> | 2018-03-06 10:07:30 +1300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2018-09-04 13:19:12 -0700 |
| commit | 718a941e19005492015ae7aa5db04d853b5af877 (patch) | |
| tree | 57393eac7a0ce279dbe7b6d1c531eee48a6692a4 /target | |
| parent | 19b599f7664b2ebfd0f405fb79c14dd241557452 (diff) | |
| download | qemu-718a941e19005492015ae7aa5db04d853b5af877.zip qemu-718a941e19005492015ae7aa5db04d853b5af877.tar.gz qemu-718a941e19005492015ae7aa5db04d853b5af877.tar.bz2 | |
RISC-V: Update address bits to support sv39 and sv48
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34abc38..e0608e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,12 +24,12 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 34 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TCG_GUEST_DEFAULT_MO 0 |