diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-12 19:14:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-21 16:31:09 +0100 |
| commit | 5d4791991d4de12e83d44738417c9e964167b6e8 (patch) | |
| tree | 2ea8dd3a34999b55f5334ba637612f8f90fc82a5 /target | |
| parent | 49c80c380d665bcc7d5b68ea1ec3617e51a90d73 (diff) | |
| download | qemu-5d4791991d4de12e83d44738417c9e964167b6e8.zip qemu-5d4791991d4de12e83d44738417c9e964167b6e8.tar.gz qemu-5d4791991d4de12e83d44738417c9e964167b6e8.tar.bz2 | |
target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
Now that we have a banked FAULTMASK register and banked exceptions,
we can implement the correct check in cpu_mmu_index() for whether
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
handlers which have requested a negative execution priority to run
with the MPU disabled. In v8M the test has to check this for the
current security state and so takes account of banking.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b67c29b..c21c592 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1498,6 +1498,21 @@ int armv7m_nvic_complete_irq(void *opaque, int irq); * (v8M ARM ARM I_PKLD.) */ int armv7m_nvic_raw_execution_priority(void *opaque); +/** + * armv7m_nvic_neg_prio_requested: return true if the requested execution + * priority is negative for the specified security state. + * @opaque: the NVIC + * @secure: the security state to test + * This corresponds to the pseudocode IsReqExecPriNeg(). + */ +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); +#else +static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +{ + return false; +} +#endif /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs @@ -2283,11 +2298,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) if (arm_feature(env, ARM_FEATURE_M)) { ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; - /* Execution priority is negative if FAULTMASK is set or - * we're in a HardFault or NMI handler. - */ - if ((env->v7m.exception > 0 && env->v7m.exception <= 3) - || env->v7m.faultmask[env->v7m.secure]) { + if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) { mmu_idx = ARMMMUIdx_MNegPri; } |