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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-14 01:32:13 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2020-12-17 10:34:59 +0100 |
| commit | ce54384405b77483f5ce06ab8dc7537299453b43 (patch) | |
| tree | b352a18c928f91bf8da72ae0f74202a78eceb81e /target | |
| parent | 388765a05bde86de9d9b66348afed6551c58f091 (diff) | |
| download | qemu-ce54384405b77483f5ce06ab8dc7537299453b43.zip qemu-ce54384405b77483f5ce06ab8dc7537299453b43.tar.gz qemu-ce54384405b77483f5ce06ab8dc7537299453b43.tar.bz2 | |
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_EQU() macro which
checks if a CPU register has bits set to a specific value.
Use the macro to check the 'Architecture Revision' level
of the Config0 register, which is '2' when the Release 6
ISA is implemented.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-5-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ac21d0..4cbc31c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -844,6 +844,7 @@ struct CPUMIPSState { #define CP0C0_MT 7 /* 9..7 */ #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ +#define CP0C0_AR_LENGTH 3 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ |