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| author | Kurban Mallachiev <mallachiev@ispras.ru> | 2017-11-29 19:22:19 +0300 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-11-30 14:56:42 +1100 |
| commit | be1b21e885743c08c921846c7201ff59fe82b8b0 (patch) | |
| tree | fca5f857b4afb63c02c5825597bd7c33c5ddf401 /target | |
| parent | 0c86b2df78fecf1d0b5017e1bab6b2607556c5ed (diff) | |
| download | qemu-be1b21e885743c08c921846c7201ff59fe82b8b0.zip qemu-be1b21e885743c08c921846c7201ff59fe82b8b0.tar.gz qemu-be1b21e885743c08c921846c7201ff59fe82b8b0.tar.bz2 | |
target-ppc: Don't invalidate non-supported msr bits
The msr invalidation code (commits 993eb and 2360b) inverts all
bits except MSR_TGPR and MSR_HVB. On non PowerPC 601 processors
this leads to incorrect change of excp_prefix in hreg_store_msr()
function. The problem is that new msr value get multiplied by msr_mask
and inverted msr does not, thus values of MSR_EP bit in new msr value
and inverted msr are distinct, so that excp_prefix changes but should
not.
Signed-off-by: Kurban Mallachiev <mallachiev@ispras.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/machine.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 24117e8..e475206 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -300,9 +300,9 @@ static int cpu_post_load(void *opaque, int version_id) ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ + /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */ msr = env->msr; - env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); hreg_compute_mem_idx(env); |