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authorPeter Maydell <peter.maydell@linaro.org>2022-08-22 14:23:52 +0100
committerRichard Henderson <richard.henderson@linaro.org>2022-09-14 11:19:40 +0100
commitb57aa7bdc3b4f16b216bd854e86431146729a640 (patch)
tree8b63275c81b01de9f43bfd8e64ffa183a17c6b91 /target
parent01765386a88868ae993bcbb39f111501fe690035 (diff)
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target/arm: Ignore PMCR.D when PMCR.LC is set
The architecture requires that if PMCR.LC is set (for a 64-bit cycle counter) then PMCR.D (which enables the clock divider so the counter ticks every 64 cycles rather than every cycle) should be ignored. We were always honouring PMCR.D; fix the bug so we correctly ignore it in this situation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822132358.3524971-5-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/helper.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a348c74..f1b20de 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1172,6 +1172,17 @@ static void pmu_update_irq(CPUARMState *env)
(env->cp15.c9_pminten & env->cp15.c9_pmovsr));
}
+static bool pmccntr_clockdiv_enabled(CPUARMState *env)
+{
+ /*
+ * Return true if the clock divider is enabled and the cycle counter
+ * is supposed to tick only once every 64 clock cycles. This is
+ * controlled by PMCR.D, but if PMCR.LC is set to enable the long
+ * (64-bit) cycle counter PMCR.D has no effect.
+ */
+ return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD;
+}
+
/*
* Ensure c15_ccnt is the guest-visible count so that operations such as
* enabling/disabling the counter or filtering, modifying the count itself,
@@ -1184,8 +1195,7 @@ static void pmccntr_op_start(CPUARMState *env)
if (pmu_counter_enabled(env, 31)) {
uint64_t eff_cycles = cycles;
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
+ if (pmccntr_clockdiv_enabled(env)) {
eff_cycles /= 64;
}
@@ -1228,8 +1238,7 @@ static void pmccntr_op_finish(CPUARMState *env)
#endif
uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
+ if (pmccntr_clockdiv_enabled(env)) {
prev_cycles /= 64;
}
env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;