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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-03-26 15:44:09 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-04-29 13:16:37 -0700 |
| commit | 8f67cd6db7375f9133d900b13b300931fbc2e1d8 (patch) | |
| tree | 0d676167fc5b6b7c973021a1d6dfc43fd02005cc /target | |
| parent | 384728905441279e54fa3d714b11bf1b1bcbfd27 (diff) | |
| download | qemu-8f67cd6db7375f9133d900b13b300931fbc2e1d8.zip qemu-8f67cd6db7375f9133d900b13b300931fbc2e1d8.tar.gz qemu-8f67cd6db7375f9133d900b13b300931fbc2e1d8.tar.bz2 | |
riscv: AND stage-1 and stage-2 protection flags
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Anup Patel <anup@brainfault.org>
Message-id: 846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com
Message-Id: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_helper.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f36d184..50e13a0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; - int prot; + int prot, prot2; bool pmp_violation = false; bool m_mode_two_stage = false; bool hs_mode_two_stage = false; @@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* Second stage lookup */ im_address = pa; - ret = get_physical_address(env, &pa, &prot, im_address, + ret = get_physical_address(env, &pa, &prot2, im_address, access_type, mmu_idx, false, true); qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot); + __func__, im_address, ret, pa, prot2); + + prot &= prot2; if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && |