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authorWeiwei Li <liweiwei@iscas.ac.cn>2022-07-18 21:09:51 +0800
committerAlistair Francis <alistair.francis@wdc.com>2022-09-07 09:18:32 +0200
commit756b0374dc37af2213e3b652fb3f50a4cc9acb24 (patch)
treee4fd2cc636b371bd7905ad97bc88bd2cce15d260 /target
parent0b572c8131998e7bcd048dbbbe78f95e6101d68d (diff)
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target/riscv: H extension depends on I extension
Add check for "H depends on an I base integer ISA with 32 x registers" which is stated at the beginning of chapter 8 of the riscv-privileged spec(draft-20220717) Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-Id: <20220718130955.11899-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b919ad9..fb37ffa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -727,6 +727,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+ error_setg(errp,
+ "H depends on an I base integer ISA with 32 x registers");
+ return;
+ }
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;