diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2022-12-14 14:27:10 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-12-15 11:18:20 +0000 |
| commit | 41654f120f535545baf91198699392376d995837 (patch) | |
| tree | 4395e362a181b2986eed44475023e7d9bcd6baf2 /target | |
| parent | e2ce5fcde468c7316b6ba3c30a970c9e50bf7211 (diff) | |
| download | qemu-41654f120f535545baf91198699392376d995837.zip qemu-41654f120f535545baf91198699392376d995837.tar.gz qemu-41654f120f535545baf91198699392376d995837.tar.bz2 | |
target/arm: Report FEAT_EVT for TCG '-cpu max'
Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu64.c | 1 | ||||
| -rw-r--r-- | target/arm/cpu_tcg.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cec6447..2cf2ca4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1254,6 +1254,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ cpu->isar.id_aa64mmfr2 = t; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9a2cef7..568cbcf 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -65,6 +65,7 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ + t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ cpu->isar.id_mmfr4 = t; t = cpu->isar.id_mmfr5; |