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authorPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:51:10 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-21 16:07:01 +0000
commit3bec78447a958d4819911252e056f29740ac25e4 (patch)
treee23d2896a011691adf82ab44913f03cb88047aff /target
parent15dd1ebda4a6ef928d484c5a4f48b8ccb7438bb2 (diff)
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target/arm: Provide ARMv8.4-PMU in '-cpu max'
Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200214175116.9164-16-peter.maydell@linaro.org
Diffstat (limited to 'target')
-rw-r--r--target/arm/cpu64.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f8f74a7..c945289 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -703,6 +703,14 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->id_mmfr3 = u;
+ u = cpu->isar.id_aa64dfr0;
+ u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+ cpu->isar.id_aa64dfr0 = u;
+
+ u = cpu->isar.id_dfr0;
+ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+ cpu->isar.id_dfr0 = u;
+
/*
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
* so do not set MVFR1.FPHP. Strictly speaking this is not legal,