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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-05-16 02:02:01 +1000 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-05-28 13:25:11 -0300 |
| commit | 277ee17212f0ac965d1fb7d65d8f938a790229ad (patch) | |
| tree | 7372b26d266c5190a3e3d9d498f1585bafc5c066 /target | |
| parent | 03ec9d9d22bb7ec81f35c1c34249d2989e7a74b4 (diff) | |
| download | qemu-277ee17212f0ac965d1fb7d65d8f938a790229ad.zip qemu-277ee17212f0ac965d1fb7d65d8f938a790229ad.tar.gz qemu-277ee17212f0ac965d1fb7d65d8f938a790229ad.tar.bz2 | |
target/ppc: Add POWER9 DD2.2 model
POWER9 DD2.1 and earlier had significant limitations when running KVM,
including lack of "mixed mode" MMU support (ability to run HPT and RPT
mode on threads of the same core), and a translation prefetch issue
which is worked around by disabling "AIL" mode for the guest.
These processors are not widely available, and it's difficult to deal
with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU
and make it the default POWER9 CPU.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-Id: <20230515160201.394587-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/cpu-models.c | 4 | ||||
| -rw-r--r-- | target/ppc/cpu-models.h | 1 | ||||
| -rw-r--r-- | target/ppc/cpu_init.c | 21 |
3 files changed, 23 insertions, 3 deletions
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 912b037..7dbb47d 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -732,6 +732,8 @@ "POWER9 v1.0") POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, "POWER9 v2.0") + POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9, + "POWER9 v2.2") POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, "POWER10 v1.0") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, @@ -907,7 +909,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "power8e", "power8e_v2.1" }, { "power8", "power8_v2.0" }, { "power8nvl", "power8nvl_v1.0" }, - { "power9", "power9_v2.0" }, + { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, #endif diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index a77e036..572b5e5 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -350,6 +350,7 @@ enum { CPU_POWERPC_POWER9_BASE = 0x004E0000, CPU_POWERPC_POWER9_DD1 = 0x004E1100, CPU_POWERPC_POWER9_DD20 = 0x004E1200, + CPU_POWERPC_POWER9_DD22 = 0x004E1202, CPU_POWERPC_POWER10_BASE = 0x00800000, CPU_POWERPC_POWER10_DD1 = 0x00801100, CPU_POWERPC_POWER10_DD20 = 0x00801200, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5aa0b3f..05bf732 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6284,9 +6284,26 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) return false; } - if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { - /* Major DD version matches to power9_v1.0 and power9_v2.0 */ + if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { + /* Major DD version does not match */ + return false; + } + + if ((pvr & 0x0f00) == 0x100) { + /* DD1.x always matches power9_v1.0 */ return true; + } else if ((pvr & 0x0f00) == 0x200) { + if ((pvr & 0xf) < 2) { + /* DD2.0, DD2.1 match power9_v2.0 */ + if ((pcc->pvr & 0xf) == 0) { + return true; + } + } else { + /* DD2.2, DD2.3 match power9_v2.2 */ + if ((pcc->pvr & 0xf) == 2) { + return true; + } + } } return false; |