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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-09-13 15:28:17 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2022-09-21 15:01:37 +0200 |
| commit | 24ec52f91dfb6d26d7035093adca60d18f02074e (patch) | |
| tree | fc67071346a4d0d5848b63fa1038a32133e3afb5 /target | |
| parent | 5934dae7a747f0aed24e8d20936ca5e117d95ad9 (diff) | |
| download | qemu-24ec52f91dfb6d26d7035093adca60d18f02074e.zip qemu-24ec52f91dfb6d26d7035093adca60d18f02074e.tar.gz qemu-24ec52f91dfb6d26d7035093adca60d18f02074e.tar.bz2 | |
target/m68k: Fix MACSR to CCR
First, we were writing to the entire SR register, instead
of only the flags portion. Second, we were not clearing C
as per the documentation (X was cleared via the 0xf mask).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target')
| -rw-r--r-- | target/m68k/translate.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ffcc761..c9bb053 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5912,8 +5912,10 @@ DISAS_INSN(from_mext) DISAS_INSN(macsr_to_ccr) { TCGv tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); - gen_helper_set_sr(cpu_env, tmp); + + /* Note that X and C are always cleared. */ + tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); + gen_helper_set_ccr(cpu_env, tmp); tcg_temp_free(tmp); set_cc_op(s, CC_OP_FLAGS); } |