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author | Max Filippov <jcmvbkbc@gmail.com> | 2020-04-06 20:59:54 -0700 |
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committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-04-07 16:08:11 -0700 |
commit | fde557ad25ff3370ef1dd0587d299a86e060bb23 (patch) | |
tree | 03efe47629182bac2fd9f54ab1942a8f22753591 /target/xtensa | |
parent | 1a03362b14affa4d8ddede55df6e21d7a07b87c2 (diff) | |
download | qemu-fde557ad25ff3370ef1dd0587d299a86e060bb23.zip qemu-fde557ad25ff3370ef1dd0587d299a86e060bb23.tar.gz qemu-fde557ad25ff3370ef1dd0587d299a86e060bb23.tar.bz2 |
target/xtensa: statically allocate xtensa_insnbufs in DisasContext
Rather than dynamically allocate, and risk failing to free
when we longjmp out of the translator, allocate the maximum
buffer size based on the maximum supported instruction length.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/xtensa')
-rw-r--r-- | target/xtensa/cpu.h | 3 | ||||
-rw-r--r-- | target/xtensa/helper.c | 1 | ||||
-rw-r--r-- | target/xtensa/translate.c | 18 |
3 files changed, 6 insertions, 16 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c0d69fa..7a46dcc 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -213,6 +213,9 @@ enum { #define MEMCTL_IL0EN 0x1 #define MAX_INSN_LENGTH 64 +#define MAX_INSNBUF_LENGTH \ + ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ + sizeof(xtensa_insnbuf_word)) #define MAX_INSN_SLOTS 32 #define MAX_OPCODE_ARGS 16 #define MAX_NAREG 64 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 376a61f..7073381 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -96,6 +96,7 @@ static void init_libisa(XtensaConfig *config) config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); + assert(xtensa_insnbuf_size(config->isa) <= MAX_INSNBUF_LENGTH); opcodes = xtensa_isa_num_opcodes(config->isa); formats = xtensa_isa_num_formats(config->isa); regfiles = xtensa_isa_num_regfiles(config->isa); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 1010c1c..e0beaf7 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -72,8 +72,8 @@ struct DisasContext { unsigned cpenable; uint32_t op_flags; - xtensa_insnbuf insnbuf; - xtensa_insnbuf slotbuf; + xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH]; + xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH]; }; static TCGv_i32 cpu_pc; @@ -1173,16 +1173,6 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE; dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >> XTENSA_TBFLAG_CALLINC_SHIFT); - - /* - * FIXME: This will leak when a failed instruction load or similar - * event causes us to longjump out of the translation loop and - * hence not clean-up in xtensa_tr_tb_stop - */ - if (dc->config->isa) { - dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa); - dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa); - } init_sar_tracker(dc); } @@ -1272,10 +1262,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); reset_sar_tracker(dc); - if (dc->config->isa) { - xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); - xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); - } if (dc->icount) { tcg_temp_free(dc->next_icount); } |