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| author | Max Filippov <jcmvbkbc@gmail.com> | 2018-04-27 13:07:53 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-06-30 11:58:02 -0700 |
| commit | f40385c959d01bf33a0e3c12ef0fdb402ad98a1c (patch) | |
| tree | 24398a0e9854be44bb97140b817723cff0a1c463 /target/xtensa | |
| parent | e3800998e66c13b24d8cc8a06fdcc8d03cd408fc (diff) | |
| download | qemu-f40385c959d01bf33a0e3c12ef0fdb402ad98a1c.zip qemu-f40385c959d01bf33a0e3c12ef0fdb402ad98a1c.tar.gz qemu-f40385c959d01bf33a0e3c12ef0fdb402ad98a1c.tar.bz2 | |
target/xtensa: check zero overhead loop alignment
ISA book documents that the first instruction of zero overhead loop
must fit completely into naturally aligned region of an instruction
fetch unit size. Check that condition and log a message if it's
violated.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa')
| -rw-r--r-- | target/xtensa/cpu.h | 1 | ||||
| -rw-r--r-- | target/xtensa/overlay_tool.h | 1 | ||||
| -rw-r--r-- | target/xtensa/translate.c | 7 |
3 files changed, 9 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e9d2e10..51b4551 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -369,6 +369,7 @@ struct XtensaConfig { unsigned nareg; int excm_level; int ndepc; + unsigned inst_fetch_width; uint32_t vecbase; uint32_t exception_vector[EXC_MAX]; unsigned ninterrupt; diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index b24ad11..ee37a04 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -456,6 +456,7 @@ .options = XTENSA_OPTIONS, \ .nareg = XCHAL_NUM_AREGS, \ .ndepc = (XCHAL_XEA_VERSION >= 2), \ + .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \ EXCEPTIONS_SECTION, \ INTERRUPTS_SECTION, \ TLB_SECTION, \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a11162e..7dd8b55 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -970,6 +970,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } dc->next_pc = dc->pc + len; + if (xtensa_option_enabled(dc->config, XTENSA_OPTION_LOOP) && + dc->lbeg == dc->pc && + ((dc->pc ^ (dc->next_pc - 1)) & -dc->config->inst_fetch_width)) { + qemu_log_mask(LOG_GUEST_ERROR, + "unaligned first instruction of a loop (pc = %08x)\n", + dc->pc); + } for (i = 1; i < len; ++i) { b[i] = cpu_ldub_code(env, dc->pc + i); } |