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authorRichard Henderson <richard.henderson@linaro.org>2022-10-24 23:09:57 +1000
committerRichard Henderson <richard.henderson@linaro.org>2022-11-01 08:31:41 +1100
commit3d419a4dd227f174447e0b3978028a1cd52ccc5e (patch)
treeb45b25a792e4d104e588b26bf0d42e29ea3a3b63 /target/xtensa
parentcc30dc441b44ad15f4adfb13d9a68cba6fa39a23 (diff)
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accel/tcg: Remove will_exit argument from cpu_restore_state
The value passed is always true, and if the target's synchronize_from_tb hook is non-trivial, not exiting may be erroneous. Reviewed-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/xtensa')
-rw-r--r--target/xtensa/helper.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index e0a9caa..2aa9777 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -253,7 +253,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs,
assert(xtensa_option_enabled(env->config,
XTENSA_OPTION_UNALIGNED_EXCEPTION));
- cpu_restore_state(CPU(cpu), retaddr, true);
+ cpu_restore_state(CPU(cpu), retaddr);
HELPER(exception_cause_vaddr)(env,
env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
addr);
@@ -284,7 +284,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else if (probe) {
return false;
} else {
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, ret, address);
}
}
@@ -297,7 +297,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc,
access_type == MMU_INST_FETCH ?
INSTR_PIF_ADDR_ERROR_CAUSE :