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| author | Max Filippov <jcmvbkbc@gmail.com> | 2017-03-06 17:17:43 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-03-13 11:30:22 -0700 |
| commit | 9fb40342d4b32152cedf32efe28b59ec3b932bd8 (patch) | |
| tree | b64f05eb2182fd569334de196445bac33c2973b4 /target/xtensa/cpu.h | |
| parent | 1b7b26e4748580dce3ec671ce7ed3d65a986cf9c (diff) | |
| download | qemu-9fb40342d4b32152cedf32efe28b59ec3b932bd8.zip qemu-9fb40342d4b32152cedf32efe28b59ec3b932bd8.tar.gz qemu-9fb40342d4b32152cedf32efe28b59ec3b932bd8.tar.bz2 | |
target/xtensa: support MTTCG
- emit TCG barriers for MEMW, EXTW, S32RI and L32AI;
- do atomic_cmpxchg_i32 for S32C1I.
Cc: Emilio G. Cota <cota@braap.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 255cc9e..d9d3b33 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,9 @@ #define ALIGNED_ONLY #define TARGET_LONG_BITS 32 +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #define CPUArchState struct CPUXtensaState #include "qemu-common.h" |