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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-04-14 14:02:17 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-14 13:19:35 -0700 |
| commit | 75eed0e5f74a05ade59b874aff3b652b5ee2e47e (patch) | |
| tree | 6fadd58727fe9a6351811bfda471c655337d6e59 /target/xtensa/cpu.h | |
| parent | 4d04ea35b30f9ba4097b746622eea07be3f2c363 (diff) | |
| download | qemu-75eed0e5f74a05ade59b874aff3b652b5ee2e47e.zip qemu-75eed0e5f74a05ade59b874aff3b652b5ee2e47e.tar.gz qemu-75eed0e5f74a05ade59b874aff3b652b5ee2e47e.tar.bz2 | |
target/xtensa: implement DIWBUI.P opcode
This is a recent addition to the set of data cache opcodes.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d6e6bf6..ba4ef2b 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -466,6 +466,7 @@ struct XtensaConfig { unsigned icache_ways; unsigned dcache_ways; + unsigned dcache_line_bytes; uint32_t memctl_mask; XtensaMemory instrom; |