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authorRichard Henderson <richard.henderson@linaro.org>2019-03-22 11:51:19 -0700
committerRichard Henderson <richard.henderson@linaro.org>2019-06-10 07:03:34 -0700
commit74433bf083b0766aba81534f92de13194f23ff3e (patch)
tree9c0c63e1d1874a47395bda07f61f160fb611c0e4 /target/xtensa/cpu.h
parent79e4208506651660b866f536616a5f8f3175f909 (diff)
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tcg: Split out target/arch/cpu-param.h
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/xtensa/cpu.h')
-rw-r--r--target/xtensa/cpu.h21
1 files changed, 5 insertions, 16 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a0df46f..0c6afd4 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -28,28 +28,17 @@
#ifndef XTENSA_CPU_H
#define XTENSA_CPU_H
-#define ALIGNED_ONLY
-#define TARGET_LONG_BITS 32
-
-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
-#define CPUArchState struct CPUXtensaState
-
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
-#define NB_MMU_MODES 4
+#define ALIGNED_ONLY
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#ifdef CONFIG_USER_ONLY
-#define TARGET_VIRT_ADDR_SPACE_BITS 30
-#else
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-#define TARGET_PAGE_BITS 12
+/* Xtensa processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
+
+#define CPUArchState struct CPUXtensaState
enum {
/* Additional instructions */