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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-03-18 17:10:38 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-10 16:53:01 -0700 |
| commit | 59419607fb340b776543f52970aefcb784eb046e (patch) | |
| tree | 5af5d3ba11c38db57ed3d6ee7e6c746ab3ce9701 /target/xtensa/cpu.h | |
| parent | efb4f3b62c69383a7308d7b739a3193e7c0ccae8 (diff) | |
| download | qemu-59419607fb340b776543f52970aefcb784eb046e.zip qemu-59419607fb340b776543f52970aefcb784eb046e.tar.gz qemu-59419607fb340b776543f52970aefcb784eb046e.tar.bz2 | |
target/xtensa: get rid of centralized SR properties
SR numbers are not unique: different Xtensa options may reuse SR number
for different purposes. Introduce generic rsr/wsr functions and xsr
template and use them instead of centralized SR access functions. Change
prototypes of specific rsr/wsr functions to match XtensaOpcodeOp and use
them instead of centralized SR access functions. Put xtensa option that
introduces SR into the second opcode description parameter and use it to
test for rsr/wsr/xsr opcode validity. Extract SR and UR names for the
xtensa_cpu_dump_state from libisa. Merge SRs and URs in the dump.
Register names of used SR/UR in init_libisa and use these names for TCG
globals referencing these SR/UR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 5d23e134..539033f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -589,6 +589,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) +void xtensa_collect_sr_names(const XtensaConfig *config); void xtensa_translate_init(void); void **xtensa_get_regfile_by_name(const char *name); void xtensa_breakpoint_handler(CPUState *cs); |