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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-03-14 10:09:15 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-03-14 10:09:15 +0000 |
| commit | 27a03171d02ee0de8de4e2d3bed241795d672859 (patch) | |
| tree | 4a3aa9eb1e3aed0e96286357e8563a15fcb1f4fa /target/sparc/translate.c | |
| parent | 5cfda4ce79dd455f1726874a555260a70f84b2ec (diff) | |
| parent | 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c (diff) | |
| download | qemu-27a03171d02ee0de8de4e2d3bed241795d672859.zip qemu-27a03171d02ee0de8de4e2d3bed241795d672859.tar.gz qemu-27a03171d02ee0de8de4e2d3bed241795d672859.tar.bz2 | |
Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const
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* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits)
tcg: Drop tcg_const_*
tcg: Drop tcg_const_*_vec
target/tricore: Use min/max for saturate
target/ppc: Avoid tcg_const_* in translate.c
target/ppc: Fix gen_tlbsx_booke206
target/ppc: Rewrite trans_ADDG6S
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
target/ppc: Avoid tcg_const_* in xxeval
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
target/ppc: Avoid tcg_const_i64 in do_vcntmb
target/m68k: Use tcg_constant_i32 in gen_ea_mode
target/arm: Avoid tcg_const_ptr in handle_rev
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
target/arm: Avoid tcg_const_* in translate-mve.c
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
target/arm: Improve trans_BFCI
target/arm: Create gen_set_rmode, gen_restore_rmode
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/sparc/translate.c')
| -rw-r--r-- | target/sparc/translate.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5ee2933..137bdc5 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2838,7 +2838,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, int width, bool cc, bool left) { - TCGv lo1, lo2, t1, t2; + TCGv lo1, lo2; uint64_t amask, tabl, tabr; int shift, imask, omask; @@ -2905,10 +2905,8 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, tcg_gen_shli_tl(lo1, lo1, shift); tcg_gen_shli_tl(lo2, lo2, shift); - t1 = tcg_const_tl(tabl); - t2 = tcg_const_tl(tabr); - tcg_gen_shr_tl(lo1, t1, lo1); - tcg_gen_shr_tl(lo2, t2, lo2); + tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); + tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); tcg_gen_andi_tl(dst, lo1, omask); tcg_gen_andi_tl(lo2, lo2, omask); @@ -2927,9 +2925,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, lo2 |= -(s1 == s2) dst &= lo2 */ - tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2); - tcg_gen_neg_tl(t1, t1); - tcg_gen_or_tl(lo2, lo2, t1); + tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2); + tcg_gen_neg_tl(lo1, lo1); + tcg_gen_or_tl(lo2, lo2, lo1); tcg_gen_and_tl(dst, dst, lo2); } |