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authorAurelien Jarno <aurelien@aurel32.net>2017-05-17 00:48:18 +0200
committerAurelien Jarno <aurelien@aurel32.net>2017-05-30 21:00:56 +0200
commit5c6f3eb7db478fe988d8419c191fe388c6cf5194 (patch)
treef111dcdde70de2ccc3275a7c90bb162f6375087e /target/sh4
parent9a562ae7ba0cadacd2fe2c8c895b0840556b978f (diff)
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target/sh4: ignore interrupts in a delay slot
Delay slots are indivisible, therefore avoid scheduling an interrupt in the delay slot. However exceptions are possible. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target/sh4')
-rw-r--r--target/sh4/helper.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 5785d6d..28d93c2 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -871,8 +871,16 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- superh_cpu_do_interrupt(cs);
- return true;
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
+ /* Delay slots are indivisible, ignore interrupts */
+ if (env->flags & DELAY_SLOT_MASK) {
+ return false;
+ } else {
+ superh_cpu_do_interrupt(cs);
+ return true;
+ }
}
return false;
}