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| author | Richard Henderson <richard.henderson@linaro.org> | 2017-10-15 19:02:42 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-10-24 22:00:13 +0200 |
| commit | 55c3ceef61fcf06fc98ddc752b7cce788ce7680b (patch) | |
| tree | 39cb3c0c16d33de6491e3dc7fa5a71933463490f /target/sh4 | |
| parent | 11f4e8f8bfaa2caaab24bef6bbbb8a0205015119 (diff) | |
| download | qemu-55c3ceef61fcf06fc98ddc752b7cce788ce7680b.zip qemu-55c3ceef61fcf06fc98ddc752b7cce788ce7680b.tar.gz qemu-55c3ceef61fcf06fc98ddc752b7cce788ce7680b.tar.bz2 | |
qom: Introduce CPUClass.tcg_initialize
Move target cpu tcg initialization to common code,
called from cpu_exec_realizefn.
Acked-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/sh4')
| -rw-r--r-- | target/sh4/cpu.c | 5 | ||||
| -rw-r--r-- | target/sh4/translate.c | 7 |
2 files changed, 1 insertions, 11 deletions
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 252440e..89abce2 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -258,10 +258,6 @@ static void superh_cpu_initfn(Object *obj) cs->env_ptr = env; env->movcal_backup_tail = &(env->movcal_backup); - - if (tcg_enabled()) { - sh4_translate_init(); - } } static const VMStateDescription vmstate_sh_cpu = { @@ -297,6 +293,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; #endif cc->disas_set_info = superh_cpu_disas_set_info; + cc->tcg_initialize = sh4_translate_init; cc->gdb_num_core_regs = 59; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8db9fba..b4e4fd3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -81,7 +81,6 @@ static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond; void sh4_translate_init(void) { int i; - static int done_init = 0; static const char * const gregnames[24] = { "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", @@ -100,10 +99,6 @@ void sh4_translate_init(void) "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", }; - if (done_init) { - return; - } - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env = cpu_env; @@ -163,8 +158,6 @@ void sh4_translate_init(void) cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, fregs[i]), fregnames[i]); - - done_init = 1; } void superh_cpu_dump_state(CPUState *cs, FILE *f, |