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authorPeter Maydell <peter.maydell@linaro.org>2022-11-24 11:50:19 +0000
committerPeter Maydell <peter.maydell@linaro.org>2022-12-16 15:58:16 +0000
commit90493830024ded23e7f9d3b383edbe74b05a6c75 (patch)
tree980ba72c45da02bfdaf649b067a34afe1960c3f9 /target/sh4/cpu.c
parent88c41e4082c01b0b06fb6d781e154deb1a4a2c83 (diff)
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target/sh4: Convert to 3-phase reset
Convert the sh4 CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-id: 20221124115023.2437291-17-peter.maydell@linaro.org
Diffstat (limited to 'target/sh4/cpu.c')
-rw-r--r--target/sh4/cpu.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 4532683..951eb6b 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -87,14 +87,16 @@ static bool superh_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
-static void superh_cpu_reset(DeviceState *dev)
+static void superh_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(dev);
+ CPUState *s = CPU(obj);
SuperHCPU *cpu = SUPERH_CPU(s);
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
CPUSH4State *env = &cpu->env;
- scc->parent_reset(dev);
+ if (scc->parent_phases.hold) {
+ scc->parent_phases.hold(obj);
+ }
memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
@@ -274,11 +276,13 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, superh_cpu_realizefn,
&scc->parent_realize);
- device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
+ &scc->parent_phases);
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;