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| author | David Hildenbrand <david@redhat.com> | 2019-03-07 13:15:37 +0100 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2019-03-11 09:31:01 +0100 |
| commit | 29b8bcf140d7f31ad38b811278074fd202ed1275 (patch) | |
| tree | 07ebe6e10705179d6c9be47851b02103cdd514ce /target/s390x | |
| parent | 7b9a236ea70f92c261206e4b120f57b0c68462cd (diff) | |
| download | qemu-29b8bcf140d7f31ad38b811278074fd202ed1275.zip qemu-29b8bcf140d7f31ad38b811278074fd202ed1275.tar.gz qemu-29b8bcf140d7f31ad38b811278074fd202ed1275.tar.bz2 | |
s390x/tcg: Implement VECTOR STORE MULTIPLE
Similar to VECTOR LOAD MULTIPLE, just the opposite direction. Probe
write access first.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190307121539.12842-31-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x')
| -rw-r--r-- | target/s390x/insn-data.def | 2 | ||||
| -rw-r--r-- | target/s390x/translate_vx.inc.c | 30 |
2 files changed, 32 insertions, 0 deletions
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index ff5b9e7..17fd9a8 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1041,6 +1041,8 @@ E(0xe709, VSTEH, VRX, V, la2, 0, 0, 0, vste, 0, ES_16, IF_VEC) E(0xe70b, VSTEF, VRX, V, la2, 0, 0, 0, vste, 0, ES_32, IF_VEC) E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC) +/* VECTOR STORE MULTIPLE */ + F(0xe73e, VSTM, VRS_a, V, la2, 0, 0, 0, vstm, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index ecc295d..0c75374 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -852,3 +852,33 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o) tcg_temp_free_i64(tmp); return DISAS_NEXT; } + +static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) +{ + const uint8_t v3 = get_field(s->fields, v3); + uint8_t v1 = get_field(s->fields, v1); + TCGv_i64 tmp; + + while (v3 < v1 || (v3 - v1 + 1) > 16) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* Probe write access before actually modifying memory */ + tmp = tcg_const_i64((v3 - v1 + 1) * 16); + gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + + for (;; v1++) { + read_vec_element_i64(tmp, v1, 0, ES_64); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + read_vec_element_i64(tmp, v1, 1, ES_64); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); + if (v1 == v3) { + break; + } + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + } + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} |