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authorPeter Maydell <peter.maydell@linaro.org>2022-11-24 11:50:18 +0000
committerPeter Maydell <peter.maydell@linaro.org>2022-12-16 15:58:16 +0000
commit88c41e4082c01b0b06fb6d781e154deb1a4a2c83 (patch)
treed0a63a40cccafaf5b31e1572fd69125a55a21ffb /target/rx
parent4fa485a78e7e887afccdd183602cfb117cf05659 (diff)
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target/rx: Convert to 3-phase reset
Convert the rx CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-id: 20221124115023.2437291-16-peter.maydell@linaro.org
Diffstat (limited to 'target/rx')
-rw-r--r--target/rx/cpu-qom.h4
-rw-r--r--target/rx/cpu.c13
2 files changed, 10 insertions, 7 deletions
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 4533759..1c8466a 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -31,7 +31,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
/*
* RXCPUClass:
* @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* A RX CPU model.
*/
@@ -41,7 +41,7 @@ struct RXCPUClass {
/*< public >*/
DeviceRealize parent_realize;
- DeviceReset parent_reset;
+ ResettablePhases parent_phases;
};
#endif
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 9003c6e..219ef28 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -62,14 +62,16 @@ static bool rx_cpu_has_work(CPUState *cs)
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
}
-static void rx_cpu_reset(DeviceState *dev)
+static void rx_cpu_reset_hold(Object *obj)
{
- RXCPU *cpu = RX_CPU(dev);
+ RXCPU *cpu = RX_CPU(obj);
RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
CPURXState *env = &cpu->env;
uint32_t *resetvec;
- rcc->parent_reset(dev);
+ if (rcc->parent_phases.hold) {
+ rcc->parent_phases.hold(obj);
+ }
memset(env, 0, offsetof(CPURXState, end_reset_fields));
@@ -215,11 +217,12 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
CPUClass *cc = CPU_CLASS(klass);
RXCPUClass *rcc = RX_CPU_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
device_class_set_parent_realize(dc, rx_cpu_realize,
&rcc->parent_realize);
- device_class_set_parent_reset(dc, rx_cpu_reset,
- &rcc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
+ &rcc->parent_phases);
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;